LT3480
7
3480fb
PIN FUNCTIONS
BD (Pin 1):
This pin connects to the anode of the boost
Schottky diode. BD also supplies current to the internal
regulator.
BOOST (Pin 2):
This pin is used to provide a drive
voltage, higher than the input voltage, to the internal bipolar
NPN power switch.
SW (Pin 3):
The SW pin is the output of the internal power
switch. Connect this pin to the inductor, catch diode and
boost capacitor.
V
IN
(Pin 4):
The V
IN
pin supplies current to the LT3480’s
internal regulator and to the internal power switch. This
pin must be locally bypassed.
RUN/SS (Pin 5):
The RUN/SS pin is used to put the
LT3480 in shutdown mode. Tie to ground to shut down
the LT3480. Tie to 2.5V or more for normal operation. If
the shutdown feature is not used, tie this pin to the V
IN
pin. RUN/SS also provides a soft-start function; see the
Applications Information section.
SYNC (Pin 6):
This is the external clock synchronization
input. Ground this pin for low ripple Burst Mode operation at
low output loads. Tie to a clock source for synchronization.
Clock edges should have rise and fall times faster than 1μs.
See synchronizing section in Applications Information.
PG (Pin 7):
The PG pin is the open collector output of an
internal comparator. PG remains low until the FB pin is
within 14% of the fi nal regulation voltage. PG output is
valid when V
IN
is above 3.6V and RUN/SS is high.
FB (Pin 8):
The LT3480 regulates the FB pin to 0.790V.
Connect the feedback resistor divider tap to this pin.
V
C
(Pin 9):
The V
C
pin is the output of the internal error
amplifi er. The voltage on this pin controls the peak switch
current. Tie an RC network from this pin to ground to
compensate the control loop.
RT (Pin 10):
Oscillator Resistor Input. Connecting a resistor
to ground from this pin sets the switching frequency.
Exposed Pad (Pin 11):
Ground. The Exposed Pad must
be soldered to PCB.
BLOCK DIAGRAM
+
–
+
–
+
–
OSCILLATOR
200kHz–2.4MHz
BurstMode
DETECT
V
C
CLAMP
SOFT-START
SLOPE COMP
R
V
IN
V
IN
RUN/SS
BOOST
SW
SWITCH
LATCH
V
C
V
OUT
C2
C3
C
F
L1
D1
DISABLE
C
C
R
C
BD
RT
R2
GND
ERROR AMP
R1
FB
R
T
C1
PG
0.7V
S
Q
3
3480 BD
4
5
10
7
1
2
3
9
11
8
6
INTERNAL 0.79V REF
SYNC
