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dc2071afc
DEMO MANUAL DC2071A
DC Power
The DC2071A requires ±16VDC and draws +100mA/
–40mA. Most of the supply current is consumed by the
CPLD, op amps, regulators and discrete logic on the board.
The +16VDC input voltage powers the ADC through LT1763
regulators which provide protection against accidental
reverse bias. Additional regulators provide power for the
CPLD and op amps. See Figure 1 for connection details.
Clock Source
You must provide a low jitter 2.5V
PP
sine or square wave
to the clock input, J1. The clock input is AC coupled so the
DC level of the clock signal is not important. A generator
like the Rohde & Schwarz SMB100A high speed clock
source is recommended. Even a good generator can start
to produce noticeable jitter at low frequencies. Therefore
it is recommended for lower sample rates to divide down
a higher frequency clock to the desired sample rate. The
ratio of clock frequency to conversion rate is 62:1 for
18-bit parts and 50:1 or 54:1 for 16-bit parts. If the clock
input is to be driven with logic, it is recommended that the
49.9Ω terminator (R3) be removed. Slow rising edges may
compromise the SNR of the converter in the presence of
high-amplitude higher frequency input signals.
Data Output
Parallel data output from this board (0V to 2.5V default),
if not connected to the DC890, can be acquired by a logic
analyzer and subsequently imported into a spreadsheet or
mathematical package depending on what form of digital
signal processing is desired. Alternatively, the data can
be fed directly into an application circuit. Use pin-50 of
P1 to latch the data. The data should be latched using the
positive edge of this signal. The data output signal levels
at P1 can also be increased to 0V to 3.3V if the application
circuit requires a higher voltage. This is accomplished by
moving JP3 to the 3.3V position.
Reference
The default reference is the LTC2373-18 internal 4.096V
reference. Alternatively, if an external reference voltage is
desired, the LTC6655-4.096 reference (U9) can be used
by setting the REF jumper (JP1) to the EXT position and
installing a 0Ω resistor in the R19 position.
Analog Inputs
The four default driver circuits for the analog inputs of the
LTC2373-18 on the DC2071A are shown in Figures 2 to 5.
The circuit of Figure 2 is a fully differential driver with
0V to 4.096V inputs. The output of this circuit is band
limited to approximately 13MHz. The circuit of Figure 3
is a single-ended to differential driver with an input signal
range of ±8.192V. This circuit is band limited to 1.6MHz
at the output. The circuit of Figure 4 is a single-ended to
differential driver with an input range of 0V to 4.096V. The
output bandwidth of this circuit is 1.6MHz. The circuit of
Figure 5 is a single-ended/fully differential input driver
circuit with an input range of ±4.096V. The input band-
width of this circuit is 4.8kHz. The output is band limited
to 3MHz. The default for this circuit is single-ended drive.
Drive the A
IN4
–
input to ±4.096V. Alternatively, by remov-
ing R117 and changing R114 to 100Ω this circuit can be
driven fully differentially.
The A
IN1
and A
IN3
driver circuits can be DC or AC coupled.
The default setting is DC coupled. AC coupling the inputs
may degrade the distortion performance of the ADC due
to nonlinearity of the coupling capacitors. AC coupling can
be implemented on the DC2071A by putting the coupling
jumpers (JP6, JP8 for A
IN1
and JP7 for A
IN3
) in the AC
position, and adding two 1kΩ resistors at the optional resis-
tor locations on the other side of each coupling capacitor
(R91, R97, R106, R110 for A
IN1
and R93, R100 for A
IN3
).
Another option available on the demo board is to drive
each input single-ended and then convert the single-ended
inputs to fully differential at the MUX outputs. This allows
the user to have eight single-ended inputs but still have
the SNR of a fully differential input. To accomplish this,
remove C31, R8, R15 and R128 then add C15, C24, C27,
C29, R7, R13, R16, R17, R18, R129, R130, R131 and
U7. The values for the passive devices are shown in the
schematic of Figure 6.
DC2071A SETUP
