16
Rev. C
For more information
APPLICATIONS INFORMATION
the ground plane as much as possible, and add thermal
vias under and near the LT8607 to additional ground
planes within the circuit board and on the bottom side.
Thermal Considerations
For higher ambient temperatures, care should be taken in
the layout of the PCB to ensure good heat sinking of the
LT8607. Figure 5 shows the recommended component
placement with trace, ground plane and via locations.
The exposed pad on the bottom of the package must be
soldered to a ground plane. This ground should be tied
to large copper layers below with thermal vias; these lay-
ers will spread heat dissipated by the LT8607. Placing
additional vias can reduce thermal resistance further. The
maximum load current should be derated as the ambient
temperature approaches the maximum junction rating.
Power dissipation within the LT8607 can be estimated
by calculating the total power loss from an efficiency
measurement and subtracting the inductor loss. The
die temperature is calculated by multiplying the LT8607
power dissipation by the thermal resistance from junction
to ambient. The LT8607 will stop switching and indicate
a fault condition if safe junction temperature is exceeded.
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Note that large,
switched currents flow in the LT8607’s V
IN
pins, GND
pins, and the input capacitor (C
IN
). The loop formed by
the input capacitor should be as small as possible by
placing the capacitor adjacent to the V
IN
and GND pins.
When using a physically large input capacitor the result-
ing loop may become too large in which case using a
small case/value capacitor placed close to the V
IN
and
GND pins plus a larger capacitor further away is pre-
ferred. These components, along with the inductor and
output capacitor, should be placed on the same side of
the circuit board, and their connections should be made
on that layer. Place a local, unbroken ground plane under
the application circuit on the layer closest to the surface
layer. The SW and BOOST nodes should be as small as
possible. Finally, keep the FB and RT nodes small so
that the ground traces will shield them from the SW and
BOOST nodes. The exposed pad on the bottom of the
package must be soldered to ground so that the pad is
connected to ground electrically and also acts as a heat
sink thermally. To keep thermal resistance low, extend
Figure 5. PCB Layout
8607 F05
GND VIA
V
IN
VIA
V
OUT
VIA
EN/UV VIA
OTHER SIGNAL VIA
C
OUT
C
IN
C
BST
C
VCC
GROUND PLANE ON LAYER 2
R
T
L
C
IN
(OPT)
R1
C
FF
R2
R4
R3
R
PG
1
C
SS
