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dc1620afb
DEMO MANUAL DC1620A
QUICK START PROCEDURE
Figure 1. DC1620 Setup (Zoom for Detail)
Analog Input Network
For optimal distortion and noise performance, the RC
network on the analog inputs may need to be optimized
for different analog input frequencies. For input frequen-
cies above 140MHz, refer to the respective ADC data sheet
for a proper input network. Other input networks may be
more appropriate for input frequencies less that 5MHz or
above 140MHz.
In almost all cases, filters will be required on both analog
the input and encode clock to provide data sheet SNR. In
the case of the DC1620A a bandpass filter used for the clock
should be used prior to the DC1075 clock divider board.
The filters should be located close to the inputs to avoid
reflections from impedance discontinuities at the driven
end of a long transmission line. Most filters do not present
50Ω outside the passband. In some cases, 3dB to 10dB
pads may be required to obtain low distortion.
If your generator cannot deliver full-scale signals without
distortion, you may benefit from a medium power amplifier
based on a Gallium Arsenide gain block prior to the final
filter. This is particularly true at higher frequencies where
IC-based operational amplifiers may be unable to deliver
the combination of low noise figure and high IP3 point
required. A high order filter can be used prior to this final
amplifier, and a relatively lower Q filter used between the
amplifier and the demo circuit.
Encode Clock
Note: Apply an encode clock to the SMA connector on
the DC1620A demonstration circuit board marked J3.
As a default, the DC1620A is populated to have a single-
ended input.
For the best noise performance, the encode input must
be driven with a very low jitter, square wave source. The
amplitude should be large, up to 3V
P-P
or 13dBm. When
using a sinusoidal signal generator a squaring circuit can
be used. Linear Technology also provides demo board
DC1075 that divides a high frequency sine wave by four,
producing a low jitter square wave for best results with
the LTC2185/LTC2145.
V
+
–
ANALOG INPUT
CHANNEL 1
PARALLEL/SERIAL
PROGRAMMING MODE
PARALLEL DATA
OUTPUT TO DC890
DUTY CYCLE
STABILIZER
SHDN
LVDS/CMOS
SINGLE-ENDED
ENCODE CLOCK
FROM DC1075
4.5V TO 6V
NAP
ANALOG INPUT
CHANNEL 2
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