SMAG + MTAG SSI
At each change of the clock signal and at each subsequent rising edge (
2
) one
bit is clocked out at a time, up to LSB, so completing the data word
transmission. The cycle ends at the last rising edge of the clock signal (
3
). This
means that up to n + 1 rising edges of the clock signals are required for each
data word transmission (where n is the bit resolution); for instance, a 13-bit
encoder needs 14 clock edges. If the number of clocks is greater than the
number of bits of the data word, then the system will send a zero (low logic
level signal) at each additional clock, zeros will either lead (LSB ALIGNED
protocol) or follow (MSB ALIGNED protocol) or lead and/or follow (TREE FORMAT
protocol) the data word. After the period Tm monoflop time, having a typical
duration of 16 µsec, calculated from the end of the clock signal transmission,
the encoder is then ready for the next transmission and therefore the data
signal is switched high.
The clock signal has a typical logic level of 5V, the same as the output signal
which has customarily a logic level of 5V in compliance with RS-422 standard.
4.3 LSB Right Aligned protocol
“LSB right aligned” protocol allows to right align the bits, beginning from MSB
(most significant bit) to LSB (least significant bit); LSB is then sent at the last
clock cycle. Transmitted bits are always 25, the sensor uses a variable number of
bits according to resolution. Unused bits are set to 0 (zero) and lead the data
word:
Model
Information
per mm
Resolution
Length of the
word
Max. number
of information
SMAG-GA-100-...
10
0.1 mm
25 bits
13 bits (8,192)
SMAG-GA-50-...
20
0.05 mm
25 bits
14 bits (16,384)
SMAG-GA-10-...
100
0.01 mm
25 bits
16 bits (65,536)
SMAG-GA-5-...
200
0.005 mm
25 bits
17 bits (131,072)
* When the profile is 650 mm / 25.59” long
See also the table on page 14
MAN SMAG GA E 1.3.odt
4 – SSI interface
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