
AMM8A SSI & BiSS C-mode
8.2 Single Cycle Data SCD
8.2.1 SCD structure
SCD data has a variable length according to the resolution of the encoder. It is
7 long where “nbitres” is the resolution of the encoder expressed in bits.
It consists of the following elements: position or speed or acceleration value
(
Position / Speed / Acceleration
) according to the
register, 1 error bit nE (
) and
a 6-bit CRC Cyclic Redundancy Check (
).
bit
7 … 8
7
6
5 … 0
function
Position
Speed
Acceleration
It is the process data transmitted from the Slave to the Master. It has a variable
length, it is as long as the resolution of the encoder expressed in bits.
It provides information about either the current position or the current speed or
the current acceleration of the encoder according to the
register: 00 = position information (default
value); 10 = speed information; 01 = acceleration information.
The transmission starts with msb (most significant bit) and ends with lsb (least
significant bit). “Nbitres” is the resolution of the encoder expressed in bits.
bit
7
...
...
8
value
msb
...
...
lsb
The bits that are not used (in case of speed and acceleration values) head the
process data and are set to 0.
For complete information refer to page 64.
Error
(1 bit)
It is intended to communicate the normal or fault status of the Slave.
When nE = “0”, an error is active in the system. For a comprehensive list of the
available error messages and their meaning please refer to the registers 74
and 76-77
nE = “1”: no active error
= “0”: error status: an error is active in the system.
MAN AMM8A SSI_BiSS E 1.10.odt
8 - BiSS C-mode interface
58 of 80
Содержание AMM8A
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