LG TCH-800, Руководство по обслуживанию

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PIN DESCRIPTION
Pin No. Symbol I/O Description
1 AVDD1 - Analog VCC1
2 DPDO O Charge pump output for Digital PLL
3 DPFIN I Filter input for Digital PLL
4 DPFOUT O Filter output for Digital PLL
5 CNTUOL I VCO control voltage for Digtial PLL
6 AVSS1 - Analog Ground1
7 DATX O Digital Audio output data
8 XIN I X’tal oscillator input
9 XOUT O X’tal oscillator output
10 WDCHO O Word clock output of 48 bit/Slot(88.2KHz)
11 LRCHO O Channel clock output of 48 bit/Slot (44.1KHz), 88.2KHz when ESP ON
12 ADATAO O Serial audio data output of 48 bit/Slot(MSB first), double speed output when ESP ON
13 DVSS1 - Digital Ground1
14 BCKO O Audio data bit clock output of 48 bit/Slot (2.1168MHz), 4.2336MHz when ESP ON
15 C2PO O C2 Pointer for output audio data
16 VREFL2 I Input terminal2 of reference voltage “L” (Floating)
17 VREFL1 I Input terminal1 of reference voltage “L” (GND connection)
18 AVDD2 - Analog VCC2
19 RCHOUT O Right-Channel audio output through D/A converter
20 LCHOUT O Left-Channel audio output through D/A converter
21 AVSS2 - Analog ground2
22 VREFH1 I Input terminal1 of reference voltage “H” (VDD connection)
23 VREFH2 I Input terminal2 of reference voltage “H” (Floating)
24 EMPH O Emphasis/Non-Emphasis output, H:Emphasis ON, L:Emphasis OFF
25 LKFS I The Lock status output of frame sync.
26 S0S1 O Output of subcode sync signal(S0+S1)
27 RESET I System reset at “L”
28 ESP I ESP function ON/OFF control (“L”:ESP function ON, “H”:ESP function OFF)
29 SQCK I Clock for output Subcode-Q data
30 SQDT O Serial output Subcode-Q data
31 SQOT O The CRC (Cycle Redundancy Check) check result signal output of Subcode-Q
32 SBCK I Clock for output subcode data
33 SDAT O Subcode serial data output
34 DVDD1 - Digital VDD1
35 MUTE I Mute control input(“H”:Mute ON)