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6. BLOCK DIAGRAM
LGE Internal Use Only
Copyright © 2007 LG Electronics. Inc. All right reserved.
Only for training and service purposes
System HW Block Diagram (Detail) : VISUAL
MSM6281
CHARGE PUM P
( BD6095 GUL)
ZR3454
MMP_RESET_ IN _ N
MMP_ CS_ N
EBI 2_ DAT A [ 0 : 15 ]
EBI 2_ OE_ N
EBI 2_ WE_ N
EBI 2 _ADDR [ 11 : 14 ]
VGA CAMERA
XENON FLAS H
8MP CAMERA
( MCB1102 - L)
LCD
SHARP
I 2 C_SCL / SDA
VGA_ CAM_PWDN/ RESET_ N
MMP_CAM_ PCLK
MMP_ CAM_HSYNC / VSYNC
MMP_CAM_ DAT A [ 0: 7 ]
CAM_MCLK
Analog
SW
MMP_ CAM_MCLK
8M_ CAM_ MCLK
CAM_ SELEC T_ N
MMP_CAM_ PCLK
MMP_ CAM_ HSYNC/ VSYNC
MMP_CAM_ DAT A [ 0: 7 ]
MMP_ CAM_RESET_ N
MMP_ I 2 C_SCL / SDA
MMP_ CAM_INT
MMP_STROB E_CHARG E
MMP_ STROB E_READY
LCD_ MMP_VSYNC_ IN
MMP_ LCD_CS_N
MMP_ LCD_RD_N
MMP_ LCD_WE_N
MMP_ LCD_ADS
MMP_ LCD_VSYNC_ OUT
MMP_ LCD_ DAT A [0: 15 ]
LCD_ IF_ MODE
LCD_ RESET_N
LCD_ MAKER_ ID
WLED_PWR
WLED_ 1/ 2/ 3 / 4 / 5
I 2 C_SCL/ SDA
CHARGEPUM P_RESET_N
CAM_ VDD_ CORE_ 1 . 2 V
CAM_ VDD_ AF_ 2 . 7 V
CAM_ VDD_ SA_ 2 . 7 V
SUB_ PM_ 2 . 7 V
CAM_ VDD_ SD_ 1 . 8 V
SUB PMIC
( BH6172 GU)
STROBE_ TRIGGER
LDO
LCD_VDD_ 2. 8 V
LCD_ LDO_EN
From MS M
VGA_VDD_ 2. 7 V
VGA_VDD_ 1. 8 V
VGA_VDD_ 2. 7V
VGA_VDD_ 1. 8V
From CHARGE PUM P
+VPWR
SUB_ PM_ 2 . 7 V
+VPWR
VREG_ MSMP_ 2 . 7 V
Analog
SW
VGA_CAM_ MCLK
From PMI C
Ambient Light
Senso r
SBIAS
SSENS
GAIN 1
GAIN 2