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Copyright © 2011 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
7. CIRCUIT DIAGRAM
C106
2.2u
1V8_VDD
1V8_VDD
VUSB
1n
C107
1V8_VDD
VBAT
75
FB101
VCORE
1V8_VDD
VDDMS
1V8_VDD
VUSB
VDDTRX
1V8_VDD
BAT101
C108
18p
1V8_VDD
1u
C109
VDDTDC
C110
220n
C111
0.1u
22u
C112
1V8_VDD
R102
12K
1V8_VDD
VDDRF2
100K
R113
VBUS_USB
47p
C113
VDDTDC
VMMC
470
R114
C115
47p
VCORE
K0
01
10
1
R
Q101
1
2
3
VRTC
VMMC
0
R115
1V8_VDD
C116
0.1u
VAUX
VAUX
C117
47p
0.1u
C118
1u
C119
VRF1
VDDMS
OJ101
VMIC
100K
R116
VBAT
3.3u
L101
VBAT
VDDXO
C120
2.2u
TP106
VDDTRX
100K
R117
18p
C121
470n
C122
UA101
12
11
10
9
8
7
6
5
4
3
2
1
GND
RX
TX
NC1
ON_SW
VBAT
NC2
NC3
NC4
DSR
RTS
CTS
GND
RX
TX
VCHAR
ON_SW
VBAT
PWR
URXD
UTXD
3G
2.5G
2V85_VSIM
VBAT_RF2
470n
C123
1V8_VDD VPMU
4.7n
C124
VBAT
47n
C125
C126
470n
47n
C127
C128
4.7n
VPMU
VBAT
VBAT
VDDRF2
0.1u
C129
U102
9
R
5
A
5
B
8
C
8
B
8
A
8
D
4
B
31
L
51
L
61
L
4
A
8
R
8T
01
F
9
E
9
C
9
B
9
D
01
E
01
D
01
C
01
B
01
A
9
A
6
E
7
G
6F
7
E
7F
6
G
8
E
7
C
6
C
7
B
7
A
5
C
6
B
6
A
2
D
1
G
1F
4
D
3
C
3
E
4F
2
E
3F
1
B
1
C
2
C
3
D
2F
1
D
1
E
9L
01
K
8L
F9
G10
H11
T1
J11
A1
F11
T16
G11
A16
C4
J12
T10
J13
P11
K16
R10
H15
H16
P13
G16
P12
J16
T13
J15
R13
H12
T12
R12
K5
G5
N15
H6
N16
H2
T14
H3
R14
H1
M16
M15
G4
G2
K15
G3
M8
T2
P9
A11
J6
B11
R3
K12
M3
K11
K4
B2
N4
A3
T3
B3
J3
A2
R2
J8
P4
H7
H4
J7
J2
H8
J4
R1
B14
C12
J1
B15
R4
B16
C13
P3
B13
P1
C14
P5
E16
N2
F16
L3
C16
L2
D16
L4
A14
K1
A15
P2
N1
R15
M2
T15
N3
M11
M1
M10
L1
N11
K2
R11
K3
T11
N12
6
K
5T
6
R
7
M
4T
6
M
6L
01
L
51
C
51
F
01
H
31
G
9
M
7L
21
F
8
P
21
E
41
G
61
R
21
A
21
B
11
E
31
H
21
G
31
A
01
J
31
F
41
F
51
P
41
P
8
G
8
K
9J
9
H
8F
9T
01
P
5
R
7
K
9
G
8
N
61
P
41
L
7
R
7T
6T
7
P
1
D
S_
D
D
V
BF
_1
D
S
1
D
S_
S
S
V
W
S_
1
D
S
S
M
S
S
V
P
ST
A
B
V
U
M
P_
T
A
B
V
1
OI
D
D
V
2
OI
D
D
V
U
B
E_
D
D
V
U
M
P
V
U
M
P_
S
S
V
1
E
R
O
C_
S
S
V
2
E
R
O
C_
S
S
V
3
E
R
O
C_
S
S
V
E
R
O
C
V
E
R
O
C
D
D
V
P
C8
V1
D
D
V
R
SL
S
S
V
X
RT
S
S
V
X
R
S
S
V
18
V1
D
D
V
P
M
A
R
V
GI
D_
S
S
V
S
M
D
D
V
O
X
D
D
V
C
DT
D
D
V
D
M
M
D
D
V
G
E
N
D
D
V
T
A
B
V
O
C
D
S
S
V
X
U
A
V
O
X
S
S
V
C
M
M
V
B
S
U
V
2F
R
D
D
V
1F
R
V
OL
_
S
S
V
F
R
S
S
V
CT
R
V
N
E
S
N
E
S
P
E
S
N
E
S
G
H
C
D
D
V
S
C
B
S
C
G
H
C
V
T
N
H
S
V
M0
M1
A_D0
M2
A_D1
VDD_FMR
A_D2
FMRIN
A_D3
FMRINX
A_D4
CP1
A_D5
CP2
A_D6
A_D7
TX1
A_D8
FE2
A_D9
RX12
A_D10
RX12X
A_D11
RX34
A_D12
RX34X
A_D13
VDET
A_D14
PABS
A_D15
PABIAS
FE1
WR_N
TX2
RD_N
PAEN
VDDTRX
A16
A17
USIF2_TXD_MTSR
A18
USIF2_RXD_MRST
A19
USIF2_RTS_N
A20
USIF2_CTS_N
A21
USIF1_TXD_MTSR
A22
USIF1_RXD_MRST
A23
USIF1_RTS_N
A24
USIF1_CTS_N
CS0_N
DPLUS
CS1_N
DMINUS
ADV_N
XOX
WAIT_N
XO
ANAMON
BFCLK0
VSIM
CC_IO
FSYS_EN
CC_CLK
CC_RST
EPN
EPP
MMCI_CMD
HSL
MMCI_DAT_0
HSR
MMCI_CLK
LSN
MMCI_DAT_1
LSP
MMCI_DAT_2
MMCI_DAT_3
MICN1
MICP1
SWIF_TXRX
MICN2
TDO
MICP2
TDI
VMIC
TMS
VUMIC
TCK
TRST_N
ACD
TRIG_IN
AGND
MON1
VREF
MON2
MON3
VSSRF2
FSYS1
NC2
FSYS2
VSSCORE4
DIGUP_CLK
NC4
DIGUP1
DIGUP2
VDDFS
N
BF
D
EL
P
BF
D
EL
V
R
D
D
EL
0
D_
FI
D
1
D_
FI
D
2
D_
FI
D
3
D_
FI
D
4
D_
FI
D
5
D_
FI
D
6
D_
FI
D
7
D_
FI
D
8
D_
FI
D
1
S
C_
FI
D
D
C_
FI
D
R
W_
FI
D
D
R_
FI
D
D
H_
FI
D
D
V_
FI
D
T
E
S
E
R_
FI
D
0
D_
FI
C
1
D_
FI
C
2
D_
FI
C
3
D_
FI
C
4
D_
FI
C
5
D_
FI
C
6
D_
FI
C
7
D_
FI
C
KL
C
P_
FI
C
C
N
Y
S
H_
FI
C
C
N
Y
S
V_
FI
C
2T
U
O
KL
C
D
P_
FI
C
T
E
S
E
R_
FI
C
0
NI
_
P
K
1
NI
_
P
K
2
NI
_
P
K
3
NI
_
P
K
4
NI
_
P
K
5
NI
_
P
K
0T
U
O_
P
K
1T
U
O_
P
K
2T
U
O_
P
K
3T
U
O_
P
K
5T
U
O_
P
K
BI
V
BI
V_
S
S
V
0T
U
O
KL
C
K2
3F
K2
3
C
S
O
N_
T
E
S
E
R
NI
2T
0
KL
C_
1
S2I
X
R_
1
S2I
XT
_1
S2I
0
A
W_
1
S2I
L
C
S_
C2I
A
D
S_
C2I
FF
O
N
O
VBAT
1V8_VDD
C130
1u
0.1u
C131
1n
C132
C133
0.1u
VDDXO
C134
0.1u
220n
C135
VBAT_RF2
62
1
R
K2.
2
VRTC
R118
3.9K
220n
C136
5.6K
R119
18p
C137
10K
R135
TP107
TP109
TP110
C139
10u
OJ102
C141
DNI
CN101
9
8
7
6
5
4
3
2
1
R138
DNI
100K
R110
1V8_VDD
47p
C142
VRF1
C143
47p
DNI
C144
R112
100K
C114
47p
R150
0
VHSMIC
2.2K
R123 R124
2.2K
1V8_VDD
32.768KHz
NX3215SA
X101
2
1
R111
56K
K0
01
52
1
R
26MHz
DSX321G-26M
X102
2
1
3
4
72
1
R
K0
01
82
1
R
K0
01
92
1
R
K0
01
U103
6
5
7
8
4
2
1
3
OUT1
IN
OUT2
EN_SET
OUT3
OUT4
GND
OUT5
DNI
R137
1V8_VDD
1u
C145
C146
1u
03
1
R
K0
01
K0
01
13
1
R
23
1
R
K0
01
K0
01
33
1
R
1V8_VDD
K0
01
43
1
R
U104
6
5
7
8
4
2
1
3
OUT1
IN
OUT2
EN_SET
OUT3
OUT4
GND
OUT5
U101
C4
C11
E7
D12
D4
E5
D10
E10
D11
E4
G3
G4
F6
F7
G8
G9
F10
F11
F4
F5
G6
G7
F8
F9
G11
G12
K14
K1
H12
H3
C12
C3
A14
A1
D9
G5
F3
E12
D5
G10
E3
H4
D7
H11
E9
E8
E11
E6
F12
D8
D6
H7
C8
C7
D3
H8
P_CRE
WAIT_
P_LB_
P_UB_
P_CE1_
CLK
WE_
OE_
AVD_
F1_CE_
F_RST_
F_WP_P_CE2
F_DPD
VCC1
VCC2
VCCQ1
VCCQ2
VSS1
VSS2
VSS3
VSS4
F_VPP
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
ADQ0
ADQ1
ADQ2
ADQ3
ADQ4
ADQ5
ADQ6
ADQ7
ADQ8
ADQ9
ADQ10
ADQ11
ADQ12
ADQ13
ADQ14
ADQ15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
C105
0.1u
1V8_VDD
100K
R109
C104
1u
R105
100K
C103
1u
100K
R107
1V8_VDD
C102
DNI
1V8_VDD
100K
R106
R104
DNI
1V8_VDD
R103
10
TP105
TP104
TP103
TP102
C101
0.1u
TP101
0
AT
A
D_
M
A
C
1
AT
A
D_
M
A
C
2
AT
A
D_
M
A
C
3
AT
A
D_
M
A
C
4
AT
A
D_
M
A
C
5
AT
A
D_
M
A
C
6
AT
A
D_
M
A
C
7
AT
A
D_
M
A
C
C
N
Y
S
H_
M
A
C
KL
C
P_
M
A
C
C
N
Y
S
V_
M
A
C
K2
3
KL
C
KL
C
M_
M
A
C
S
R_
D
CL
S
C_
NI
A
M_
D
CL
N
00
AT
A
D_
D
CL
10
AT
A
D_
D
CL
20
AT
A
D_
D
CL
30
AT
A
D_
D
CL
40
AT
A
D_
D
CL
50
AT
A
D_
D
CL
60
AT
A
D_
D
CL
70
AT
A
D_
D
CL
Y
B
D
N
AT
S_
M
A
C
N
E_
G
H
C
T
NI
_T
B_
B
B
D
C
N
Y
S
V_
D
CL
R
W_
D
CL
N
T
NI
_
B
B
D_
T
B
T
NI
_
CI
U
M
BS2
BT_CLK
I2C_SCL
I2C_SDA
PCM_CLK
X
R_
M
C
P
XT
_
M
C
P
PCM_SYNC
S
C_I
P
S
FM_LNA_EN
T
C
ET
E
D_
K
O
O
H
T
E
D_
D
S
U
LCD_ID
BAT_TEMP
HS_MIC_N
USD_CLK
USD_CMD
USD_D1
USD_D2
USD_D3
BS1
TX_EN
RX12
RX12X
RX34
RX34X
DCS_PCS_OUT
ST
C_
T
B
ST
R_
T
B
BT_RXD
BT_TXD
TX_RAMP
TDO
TDO
TCK
TCK
TMS
TMS
TDI
TDI
LDO_OUT
USB_DP
USB_DM
PWRON
PWRON
AD22
AD22
AD21
AD21
AD20
AD20
AD19
AD19
AD18
AD18
AD17
AD17
AD16
AD16
MEM_CLK
MEM_CLK
NWAIT
NWAIT
AD15
AD15
AD14
AD14
AD13
AD13
AD12
AD12
AD11
AD11
AD10
AD10
AD09
AD09
AD08
AD08
AD07
AD07
AD06
AD06
AD05
AD05
AD04
AD04
AD03
AD03
AD02
AD02
AD01
AD01
AD00
AD00
NADV
NADV
NRAM_CS
NRAM_CS
NRD
NRD
NWR
NWR
NRESET
NRESET
T
E
S
E
R
N
NROM_CS
NROM_CS
UART_TX
UART_TX
UART_TX
UART_RX
UART_RX
UART_RX
EPN
EPP
F_BOOT
T
O
O
B_
F
NTRST
NTRST
C
O
E_
USD_D0
NLB
NLB
NLB
NUB
NUB
AD23
AD23
AD24
AD24
JACK_DETECT
2L
O
C_
Y
E
K
1
W
O
R_
Y
E
K
3L
O
C_
Y
E
K
LCD_BL_CTRL
LCD_BL_CTRL
SPI_CLK
T
NI
_I
P
S
SPI_MISO
BT_RESET
BT_RESET
SIM_DATA
SIM_CLK
SIM_RST
IO_EXPANDER1
IO_EXPANDER1
HSL
HSR
M
W
P_
BI
V
LCD_RESET
3
W
O
R_
Y
E
K
2
W
O
R_
Y
E
K
IO_EXPANDER0
IO_EXPANDER0
VIB_EN
WLAN_RESET
MIC_P
TOUCH_EN
CAM_RESET
BS3
HS_MIC_P
T
NI
_
H
C
U
OT
WLAN_REG_ON
MIC_N
SPI_MOSI
F_MODE
F_MODE
FSYS_EN
GSM_OUT
FM_ANT_2
MIC_GND
CT
R_
D
D
V
ABB
RF
RF
5T
NI
E
INT PORT
0T
NI
E
VDDP_SIM
BT_DBB_INT
DIF_RESET
EINT4
LIGHT BLUE
RF PADS
(SUPER CAP)
USIF1_CTS_N
VDDP_DIG1
(10V)
PIN_H10
PIN COLOR DESCRIPTION
EINT4/EINT1
SIGNAL CHECK
Seperate and shield
Speaker Supply
(10V)
6T
NI
E
_CHG_EOC
VDD_IO2
PLACE THESE CAPS NEAR BB IC
Close to the 26MHz XTAL
VBATSP
SLIDE
T2IN
SIGNAL NAME
DIGUP2
BACKUP BATTERY
ABB
VDDP_DIG1
MUIC_INT
CC0CC1IO
ON BOARD ARM9 JTAG & ETM INTERFACE
(1%)
0T
NI
E
ABB PADS
VDDP_EBU
CC0CC1IO
PMU PADS
RF SUPPLY DOMAIN
VDDP_DIG1
VDDP_MMC
DBB SUPPLIES
4T
NI
E
VDD1V8CP
EINT2
VDD_IO1
1T
NI
E
EINT7
CC1CC6IO
EINT0
PIN NAME
PIN_H13
PIN_B14
RF SUPPLIES (DIRTY GND)
ORANGE
PMU SUPPLIES
PIN K8
PIN M9
PIN L7
PIN P8
VDDP_DIG1
VDDP_ULPI
RF SUPPLIES (CLEAN GND)
(NOT MOUNTED)
1T
NI
E
VDDP_DIG1
uSD_DET
(10V)
YELLOW
7T
NI
E
VBAT_PMU
PIN P14
PIN P16
CC1CC6IO
USIF1_RTS_N
PIN P10
PIN R5
PIN G9
1
GI
D_
P
D
D
V
VDDP_DIG2
VDDP_DIG1
EINT3
Connect GND plane directly
CN101 : SW DEBUG
6T
NI
E
PIN_B12
PIN_E11
PIN_G14
PIN_G13
UART PORT
CC0CC7IO
OI
3
C
C1
C
C
ABB SUPPLIES
DBB SUPPLIES
PIN K7
PIN N8
(FOR SW DEBUGGING / NOT MOUNTED)
VDD_EBU
0T
NI
E
RF
DBB SIGNAL PADS
MAGENTA
PMU PADS
LIGHT GREEN
OI
4
C
C1
C
C
ON BOARD UART/USB INTERFACE
MEMORY(1G NOR/256 pSRAM,56 balls)
7. CIRCUIT DIAGRAM