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Copyright © 2010 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
3. TECHNICAL BRIEF
snTzZXWGGG
clock output
D
AE12
LSCE0B
VDD33_LCD
IO
Serial display interface
chip select 0 output
GPIO27
LSCE0B
CLKM2
TCTIRQ
2
PU/P
D
PU
AC12
LSCE1B
VDD33_LCD
IO
Serial display interface
chip select 1 output
GPIO28
LSCE1B
LPCE2B
TCTIRQ
1
PU/P
D
PU
AB12
LPCE1B
VDD33_LCD
IO
Parallel display
interface chip select 1
output
GPIO29
LPCE1B
NCE1B
TEVTVA
L
PU/P
D
PU
AE13
LPTE
VDD33_LCD
IO
͑
GPIO30
LPTE
͑
͑
PU/P
D
PD
AD14
NLD17
VDD33_LCD
IO
Parallel LCD/NAND-
Flash Data 17
GPIO31
NLD17
͑
͑
PU/P
D
PD
AC14
NLD16
VDD33_LCD
IO
Parallel LCD/NAND-
Flash Data 16
GPIO32
NLD16
͑
͑
PU/P
D
PD
AC18
NRNB
VDD33_LCD
IO
NAND-Flash
Read/Busy Flag
GPIO33
NRNB
͑
͑
PU/P
D
PU
AB18
NCLE
VDD33_LCD
IO
NAND-Flash
Command Latch
Signal
GPIO34
NCLE
͑
͑
PU/P
D
͑
AE19
NALE
VDD33_LCD
IO
NAND-Flash Address
Latch Signal
GPIO35
NALE
͑
͑
PU/P
D
͑
AD19
NWEB
VDD33_LCD
IO
NAND-Flash Write
Strobe
GPIO36
NWEB
͑
͑
PU/P
D
͑
AC19
NREB
VDD33_LCD
IO
NAND-Flash Read
Strobe
GPIO37
NREB
͑
͑
PU/P
D
͑
AB19
NCEB
VDD33_LCD
IO
NAND-Flash Chip
select output
GPIO38
NCE0B
͑
͑
PU/P
D
͑
U10
SRCLKEN
AN
VDD33
IO
External TCXO enable
output active low
GPIO42
SRCLK
ENAN
͑
͑
PU/P
D
͑
AE11
SRCLKEN
A
VDD33
IO
External TCXO enable
output active high
GPIO41
SRCLK
ENA
͑
͑
PU/P
D
͑
AD11
SRCLKEN
AI
VDD33
IO
External TCXO enable
input
GPIO43
SRCLKE
NAI
͑
͑
PU/P
D
PD
A22
KCOL7
VDD33
IO
Keypad column 7
GPIO55
KCOL7
IRDA_P
͑
PU/P
PU
Содержание LG-S310
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