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LGE Internal Use Only
Copyright © 2010 LG Electronics. Inc. All right reserved.
Only for training and service purposes
3. TECHNICAL BRIEF
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3.4.6 GPIO Map
Ball
͑
PU/
PD
Res
et
13X13
Name
Power
Domain
Dir
Description
Mode0
Mode
1
Mode
2
Mode
3
AC6
BPI_BUS
3
VDD33
IO
RF hard-wire
control bus 3
GPIO19
BPI_B
US3
͑
͑
PU/
PD
PD
AC8
BPI_BUS
6
VDD33
IO
RF hard-wire
control bus 6
GPIO20
BPI_B
US6
͑
͑
PU/
PD
PD
AB8
BPI_BUS
7
VDD33
IO
RF hard-wire
control bus 7
GPIO21
BPI_B
US7
͑
͑
PU/
PD
PD
AE9
BPI_BUS
8
VDD33
IO
RF hard-wire
control bus 8
GPIO22
BPI_B
US8
͑
͑
PU/
PD
PD
AD9
BPI_BUS9
VDD33
IO
RF hard-wire control
bus 9
GPIO23
BPI_BU
S9
BSI_CS
1
͑
PU/P
D
PD
AC10
PWM0
VDD33
IO
Pulse width
modulated signal 0
GPIO39
PWM0
͑
͑
PU/P
D
PD
AB10
PWM1
VDD33
IO
Pulse width
modulated signal 1
GPIO40
PWM1
BSI_RFI
N
͑
PU/P
D
PD
AC5
PWM2
VDD33_CAM
IO
Pulse width
modulated signal 2
GPIO17
PWM2
͑
D2_TID
5
PU/P
D
PD
AE5
PWM3
VDD33_CAM
IO
Pulse width
modulated signal 3
GPIO18
PWM3
͑
D2_TID
6
PU/P
D
PD
AE4
SCL
VDD33_CAM
IO
͑
GPIO15
SCL
͑
D2_TID
3
PU/P
D
PU
AD5
SDA
VDD33_CAM
IO
͑
GPIO16
SDA
͑
D2_TID
4
PU/P
D
PU
AC11
LSCK
VDD33_LCD
IO
Serial display interface
data output
GPIO24
LSCK
DSP_G
PO2
IRQ0
PU/P
D
PD
U11
LSA0
VDD33_LCD
IO
Serial display interface
address output
GPIO25
LSA0
DSP_G
PO3
IRQ1
PU/P
D
PD
AD12
LSDA
VDD33_LCD
IO
Serial display interface
GPIO26
LSDA
CLKM1
TDTIRQ PU/P
PD
3.4.6 GPIO Map
Содержание LG-S310
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