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Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
7. HDMI BLOCK DIAGRAM
Audio processing
HDMI packet insertion
HDCP block
TMDS block
I2C DDC interface
Video processing
PLL block
PCLK
ACLK
TXclkp
TXclkn
TX0p
TX0n
TX1p
TX1n
TX2p
TX2n
EXT_
swing
DSCL
DSDA
SCL
SDA
I2C slave
DDC master
HDCP
processing
OTP memory
keys
Data island
packet insertion
VHREF generatior
Audio content
Info Frame
ACR
Null & ACP
CTS/N
FIFO
Audio capture
processing
Clock
Management
RxSense
HDMI
Serializer
Down- sampler 4:4:4 to 4:2:2
(1)
Up-
sampler 4:2:2
To 4:4:4
Up-Scaler
4:2:2
Video input data capture
3x8 bit YCbCr/RGB 4:4:4 2x12 bit YCbCr 4:4:2
2x12 bit
YCbCr
(1) Can be bypassed
Color space converter RGB to YUV YUV to RGB
(1)
Registers
WS
AP[3..0]
MCLK
SPDIF
AUX
VSYNC
HSYNC
DE
VA[7..0]
VB[7..0]
VC[7..0]