XI
XO
CRYSTAL CIRCUIT
C204
1000pF/NC
C204
1000pF/NC
R201
100K
R201
100K
R268
0
R268
0
L209
2.7uH/NC
L209
2.7uH/NC
R269
0
R269
0
Y201
27M
Y201
27M
1
2
3
C212
27pF
C212
27pF
C232
27pF
C232
27pF
3-10
Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
DETAILS AND WAVEFORMS ON SYSTEM TEST AND DEBUGGING
1. SYSTEM 27MHz CLOCK, RESET, FLASH SCK SIGNAL.
1-1. 1389DE/LP main clock is at 27MHz(Y201)
1-2. 1389DE/LP reset is active high.
FIG 1-1
1
3.3V
V18
+
CE208
100uF/6.3V
+
CE208
100uF/6.3V
1
2
R230
330
R230
330
C236
0.1uF
C236
0.1uF
L207
FB(1206)
L207
FB(1206)
R223
680
R223
680
U202
CM1117SCM233
SOT223
U202
CM1117SCM233
SOT223
OUT
2
IN
3
ADJ
1
TAB
4
+
CE209
100uF/6.3V
+
CE209
100uF/6.3V
1
2
URST#
DV33
L213
10uH
L213
10uH
+
CE213
22uF/16V
+
CE213
22uF/16V
1
2
R236
22K
R236
22K
B
C
E
Q202
3904
B
C
E
Q202
3904
1
3
2
R225
3.3K
R225
3.3K
L214
10uH
L214
10uH
D201
1N4148/NC
D201
1N4148/NC
1
2
B
C
E
Q201
3904
B
C
E
Q201
3904
1
3
2
R224
3.3K
R224
3.3K
R235
4.7K
R235
4.7K
R226
15K
R226
15K
FIG 1-2
2
3
3
2
1
1.8V
RESET