Lexicon MPX 110, Руководство по обслуживанию

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MPX 110 Service Manual
6-6
During power up while RESET/ is asserted low, bringing U7 pin 1 high enables the feedback oscillator. The
oscillator's output is selected as the ZCLK, and ZRST is held low by U6.
When the RESET/ signal goes high, the feedback oscillator is disabled as U7 pin 1 is brought low, the
ZCLK_LEXI3 clock (from the Lexichip 3) signal is selected as the ZCLK, and ZRST is controlled by
ZRST_LEXI3 signal (from the Lexichip 3).
Sheet 5
ENCODERS
The rotary encoder is 16 position, 4 bits. Gray code is generated in the following clockwise rotation
sequence (hexadecimal, terminals 1-4): 0,1,3,2,6,7,5,4,C,D,F,E,A,B,9,8. It is necessary to have pull-up
resistors at the Front Panel encoders (SW3 and SW4). RP1 & RP3 pull up the inputs, this prevents Lexichip
3 inputs from floating and provides a default non-active switch state of logic high. ??
Sheet 6
CONTROL INPUT (IAD)
The pot A/D converter is the integrating type made from current source Q5 and 8-bit timer in the Lexichip 3.
To start the conversion, the Z80 tells the Lexichip 3 to bring RESET_IAD high, which toggles U13 and
discharges capacitor C44 to less than 0.2V. Next the Z80 selects which pot (ADMUXIN0 - 3) the Lexichip 3
will digitize. It does this by writing to a IAD mux register in the Lexichip 3.
The Lexichip 3 then starts its timer and brings RESET_IAD low. C44 starts to charge from the current
source. Once the capacitor voltage exceeds the pot voltage, the muxed comparator output goes low. This
produces a high level interrupt to the Z80, which disables the timer. At its convenience the Z80 reads the
timer and derives the voltage on the pot. R44 sets input voltage range from 0-3V. This voltage is also the
calibration voltage for the IAD, it will guaranty the pots full range will be used regardless of fluctuation in
voltage and temperature.
Sheet 7:
FOOTSWITCH
Footswitch jack J2 use resistors (R9, R11) and capacitors (C8, C9) to filter out RFI. D10 and D11 help
protect from over voltage or static shock and R12 and R10 provide a default non-active switch state of logic
high.
LED/SWITCH MATRIX
There are eight discrete LED’s on the front panel, which are organized into 2 columns and 4 rows.
An octal D-Flop U2 clocks the data bus on the rising edge of CTL_REG/. ZD4 creates (COLUMN_STRB0)
and ZD5 creates (COLUMN_STRB1). These column select lines are active low. These are buffered and
inverted by switching transistors Q2 and Q3. When COLUMN_STRB0 line is driven low, net line “col0” is
high and if DSPLY_ROW0 line is driven low, then LED D18 will light. In this configuration, if SW1 “TAP”
switch is pressed, the SWITCH_ROW0 signal will go high. R28 pull down will hold the SWITCH_ROW0
signal to ground when the switch is not pressed.
Row lines are driven directly from U2 (sheet 4). U2 is only driving four lines, so the total current in the IC
remains well below 100mA. The 100-330 Ohm resistors (R16-R19) limit the row current to about 28mA or
less. The variance in resistor values is an adjustment for brightness.