Lexicon 200, Руководство по обслуживанию, Страница: 44 / 90

MPX 200 Service Manual
6-8
Chip Select Buffers
U22 currently is the only chip select buffer used on the MPX200. Provision has been made to add a second
one (U21) in order to separate out read from write chip selects, but this has not been implemented. Resistor
R154 guarantees that chip select signal REG_SEL/ is held in an inactive state during power up. R157
merely acts as an enable for the chip itself. Resistors R139 through R141 provide RFI protection by slowing
down the edge rates of signals ROW_REG_0/, ROW_REG_1/, and ROW_REG_2/.
Signal REG_SEL/ qualifies each chip select at a base address of 0x4C00 with the three address lines
ZA[2:0]. In other words, whatever the binary value of ZA[2:0], if it is added to 0x4C00 the address decode
for each chip select output may be derived.
ZA[2:0] Value Address Active Chip Select
000 0x4C00 STAT_RD/
001 0x4C01 SP_STAT/
010 0x4C02 ROW_REG_0/
011 0x4C03 ROW_REG_1/
100 0x4C04 ROW_REG_2/
101 0x4C05 Test Point E7
110 0x4C06 Test Point E6
111 0x4C07 Test Point E8
Sheet 6
This sheet shows the all the impedimenta necessary to implement DSP algorithms. These are comprised of
the Lexichip3, the Audio Memory, and the clock oscillator.
Lexichip3
Configuration resistors R83-R90 set the operating mode of the Lexichip3 via the internal data bus ZD[7:0]
when the RESET/ is released. The resistors set this configuration constant as follows:
ZD Bits
7 6 5 4:2 1:0
Resistor R86 R83 R87 R84, R88, R89 R85, R90
Set 0 0 0 010 00
Function CHIP_TRST EXTMCX EXTM ZCLKSEL HADEC
CHIP_TRST: The unidirectional output buffers are enabled for normal operation.
EXTMCX2: Source MCX2 (8X XTAL Frequency) from internal PLL..
EXTMC: Generate MC (Masterclock) Internally.
ZCLKSEL: Z80 ZCLK = PLL Clock Divided by 10 (ZCLK clock-tree output).
HADEC: Select Z80 Address Map 0 (More details below).
ADDRESS MAP 0
0000 - 3FFF
16K Common ROM (ZDEC0/)
4000 - 4BFF 3K Lexichip3 Internal Decodes*
4C00 - 4FFF 1K Expansion Area (ZDEC2/)
5000 - 5FFF 4K Common SRAM (ZDEC1/) (* note 3)
6000 - 7FFF 8K Bank-Swapped SRAM (1-16 Banks, 8KB - 128KB) (ZDEC1/)
8000 - FFFF 32K Bank-Swapped ROM (1-16 Banks, 32KB - 512KB) (ZDEC0/)
If any chip on the Z80 data bus erroneously drives the data bus during RESET/, the Lexichip3 will come up
in the wrong mode and the Z80 will not function properly. Therefore, during RESET/, all the relevant chip