Lexicon 200, Руководство по обслуживанию

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Lexicon
6-7
and the AK4112A. R64 is a provision for bypassing the U14 circuitry, but it is not implemented in this
design.
Front Panel Connector
The front panel connector is not precisely a connector. Rather, it is a 16 x 1 row of solder pads that accept
a semi-rigid flat cable that solders directly to the Main PCB and the Front Panel PCB.
FB3 and C94 provide filtering of the power supply going up to the front panel. Because of the high current
demand of the front panel board, and the multiplexing nature of LED activity, FB3 provides a high
impedance to switching noise that would otherwise find it’s way into the supply lines to critical circuitry on
the main board. C94 provides a charge reservoir to meet the demand of the current supplied to the LEDs.
SWITCH_ROW1/ is a logical OR signal of the Bypass, Edit, and Tap/Cancel switches on the front panel.
SWITCH_ROW0/ is a logical OR signal of the Store, Compressor, and Load switches on the front panel.
ROW_REG[2:0]/ are address decoded strobes for three registers on the front panel board. Further
enhancement and address mapping of these strobes will be provided in the walk-through for the Front
Panel PCB.
FP_RESET/ is as the name implies; an active low reset signal for the front panel registers. R130 through
R138 provide edge rate limitations of the data buss and reset signal going off the main PCB. This is done to
aid in RFI elimination.
ZD[7:0] is an eight bit wide data bus that functions as a control for lighting the 60 LED segments that
populate the front panel. This number includes each segment of three seven-segment displays installed on
the front panel.
Sheet 5
This sheet shows the Z80 processor, memory interface, user program storage, flash ROM, and chip select
buffers used throughout the design.
Z80, Memory, Flash, and User Program Storage
The Z80 (U19) handles all basic system control and user interface I/O operation. Normally, the Z80 clock
ZCLK is derived from the Lexichip3 M_ZCLK pin, via multiplexor U9. However, when RESET/ is asserted,
before the Lexichip3 is functioning, U9 feeds a clock signal generated by U14, R81, and C74. Resistors
R80 provides protection from RFI. R82 is a provision for further RFI protection; currently all that is required
is a 0 ohm resistor. Also during power up reset, U9 hardwires a logic low into the RST/ pin of the Z80; this
ensures that the Z80 remains at a hard reset during this time. The Z80 interrupt signal ZINT/ is pulled high
by R142 to ensure that the Z80 receives no false interrupt indications during power up. This is a weak pull-
up and has no effect during normal operation. The Lexichip3 master clock (CLK_IN, pin 75), is driven by an
11.2896MHz crystal. All the system software and programs are stored in 256Kx8 Flash ROM (U20).
Resistors R143 through R145 ensure that the default states of ROM_A16, ROM_A17, and ROM_EN/ are
inactive; ROM_A[16:17] are pulled inactive low while ROM_EN/ is pulled inactive high. The Z80’s memory
is a 8Kx8 SRAM (U16). User programs are stored in a 4kx8 serial EEPROM (U8). The serial data line
(SERIAL_DATA) is bi-directional. R66 prevents excessive current in either the EEPROM or the Lexichip3
during power-up, when both chips might drive the line. R67 provides pull-up for this data line while R65
provides a pull-up for the EEPROM_CLK. The audio memory for the Lexichip3 is provided by 1Mx16 DRAM
(U17) Located on Sheet 6. Note that all address decoding (RAM_EN/, ROM_EN/, etc.) is done within the
Lexichip3. That is the primary reason the Z80 cannot function if the Lexichip3 is improperly initialized at the
rising edge of RESET/.