Operations Manual DA924
7
1. The unit goes into mute mode.
2. Warm-up: An internal oven heats up the temperature-sensitive devices to a set
temperature. The warm-up time depends on the initial temperature and may take up to 5
minutes for a cold unit. During warm-up, the unit blinks the two upper status lamps (44.1
and 48 light emitting diodes).
3. When set temperature is reached, the unit goes into self calibration mode. The calibration
time may take a few minutes. During calibration, the unit blinks the two lower status lamps
(88.2 and 96 light emitting diodes).
4. The unit finds the first active input and converts digital audio to analog sound.
The DA924 figures out the incoming sample rate for the selected input and displays the
incoming frequency (44.1, 48, 88.2 or 96KHz). When all inputs are inactive, the unit
steps through the input ports continuously as indicated by the input select lamps if in auto
select mode.
Most DACs contains relays for the purpose of muting the output during turn on (allowing
the DAC to settle to proper operating conditions). The DA924 contains no relays, in order
to avoid signal degradation associated with relay contacts. The unit deals with the turn on
spike by incorporating very slow tracking power supplies for its output stage, thus
disabling the drive capability during turn on. The DA924 turn on spike may be higher then
that found in other DACs but the sound is not compromised. The spike due to power off is
comparable to that found in other DACs.
Polarity inversion
The normal polarity is set to pin 3 hot. To invert, press the POLARITY switch. Signal
inversion is indicated by a lit INVERT lamp.
Inverting while in unbalanced operation impacts signal polarity on the IEC center
conductor.
Inverting while in unbalanced operation impacts signal polarity on pin 2 of the XLR
connector.
Inverting while in balanced operation swaps pin 2 and pin 3 of the XLR connector.
CrystalLock™ and Wide lock
The DA924 eliminates jitter in the incoming data stream by use CrystalLock™, a DSP
controlled pullable crystal oscillator and a short buffer memory for temporary storage of the
incoming data. The DSP transfers the data from the memory to the DAC disregarding any
jitter in the input frequency. A proprietary fast-lock high-accuracy measurement compares
the average input frequency to the oscillator frequency and makes the appropriate
adjustments. The adjustments are done with sub pico-second resolution, to insure
minimum interference with signal reconstruction.
CrystalLock™ meets and exceeds the AES lock range requirements ( +/- 100ppm). Such
narrow lock allows the use of pullable crystal oscillators, thus yielding the best
performance from a jitter standpoint. The DA924 provides a wide lock mode for tracking
sample rates between 40 and 50KHz, and 86 and 98kHz. Clock jitter levels increase when
