DA924
Operations Manual
10
cycle consists of reading and adjusting of all the nodes. The processor repeats the
calibration cycle numerous times until all the nodes are set properly. Though nodes
interaction exist during the adjustment process, the overall network is guaranteed to
converge on a solution by design. Calibrating a DA924 for the first time (at the factory)
often exceeds 25 minutes. Once calibrated, the settings are stored in non volatile ram for
future startup point of reference, thus all future adjustments are initialized to the last
settings. Therefore the initial tolerance of the components is pre calibrated already, and each
new calibration needs to deal only with component drift under the same given temperature
conditions (ovenized components). The remaining calibration at each subsequent power on
takes less then 2 minutes typically.
Timing and deglitcher
The conversion from a digital sample value to an analog voltage consists of translating a
digital code to a corresponding setting of analog switches and multiplexers to tap the
appropriate voltage from the analog nodes. Such switching causes unwanted glitch energy
to come into play. The glitch energy is code and signal dependent and can not be removed
by filtering. The purpose of the deglitcher circuit (see diagram) is to block the signal from
feeding to the output for long enough time after each transition, thus allowing the glitches
enough time to disappear, and for each new analog sample to accurately settle to its final
value.
The deglitcher circuit is in off state about half a sample time, and on for the rest of the time.
The on time, is the critical time and no digital activity takes place anywhere near the analog
circuits. The settled signals are fed to the output filter with minimum disturbance. The
deglitcher off time settling requires the circuit to block as much of the transitions from
feeding forwards to the output filter.
The blocking requirement is very demanding because a transition of many volts between
two adjacent sample values should feed forward less than a micro volt. A single switch can
not yield such blocking performance. The deglitcher utilizes four switches: the first switch
shunt (shorts) the signal to ground. The remaining signal is connected to the second switch
that is in open state. Whatever comes through gets shunted to ground be the third switch.
The remaining tiny energy is further blocked by the fourth opened series switch.
During the deglitcher on state, the shunt switches (switch one and three) are opened and the
series switches (switch two and four) are shorted to allow the signal path to the output. The
deglither circuit utilizes DMOS technology thus providing extremely low resistance during
the on state. The remaining problems due to on state resistance variations is neutralized by
use of the strong feedback of the deglitcher amplifier.
The main reason for using DMOS transistors is their sub nanosecond switching
capabilities. The jitter critical timing point is all at the deglitcher circuit. Each sample value
must exist over the same time period thus precise deglitcher turn on and turn off are critical
for good results. In fact switching during deglitcher blocking time can be somewhat
sloppy, as long as the signals are well settled prior to turn on. Fighting the jitter wars
means feeding the deglitcher circuit a precise jitter free on / off drive signal.
Jitter removal
Ordinary phase lock loops circuits (PLLs) do a reasonable job at removing high frequency
jitter from the incoming clock. The same circuits perform very poorly in the removal of low
