Operations Manual DA924
11
frequency jitter from the clock signal. The need to keep enough bandwidth for locking to
and tracking the incoming data translates to zero rejection of low frequency jitter content
(typically hundreds of Hz of zero rejection bandwidth). While some of the jitter content is
random, much is due to coupling of the data itself into the receiver circuitry.
The DA924 uses a non standard approach for removing jitter. The deglitcher circuit is
clocked by a pullable crystal oscillator but the control signal for the crystal is freed from
having to track down incoming clock variations. The clock oscillator is controlled by a
processor driven DAC (not an ordinary phase detector plus filter circuit). The oscillator
frequency is change by tiny amounts (.1ppm) and not very often (15 seconds or more) in a
manner allowing it to track only very long term average drift. Using such an approach with
ordinary PLL will cause loss of lock because the slight variations in incoming data rate
cause loss of correspondence between the input and the too steady of a clock circuit. The
DA924 CrystalLock (TM) approach, stores enough data in a dedicated memory to
guarantee that each clock cycle can find its data. Moving the clock slowly to track the long
term average drift is done just fast enough to make sure that the buffer memory does not
overfill or becomes empty.
At first glance one may get concerned about the potential long delay due to storage of a lot
of data samples. In fact, the data storage is very small and so is the delay. An "unrealistic"
100ppm per second input rate step requires pre storage of about 5 words of data for 1
second D/A stepping, or an 50 word memory for 10 seconds of D/A update rate.
Output filter and drivers
The DA924 operates in low oversampling to allow for maximum settling time of the DAC
circuits and to further reduce sensitivity to jitter. The upsampling filter is calculated by the
DSP. The tradeoff in favor of low oversampling operation pauses an increased requirement
for analog anti imaging filtering. The DA924 incorporates a seven pole analog filter.
The transistor based output drivers are short circuit protected and are capable of driving
balanced 300 Ohm loads. As always, for best results it is recommended to use high quality
cables. When running a cable through an electrically noisy environment, a termination
impedance of 600 Ohms (at the destination, not at the DA924 side) may prove useful .
Power and Fusing
The Model DA924 operates at 50 or 60 Hz, and has two line voltage selections, 115 volts
and 220 volts, switchable on the back panel. 115 volts operation requires a 1/2 ampere 250
volt fast blow fuse; 220 volt operation requires 1/4 ampere 250 volt fast blow fuse. Both
American and European size fuses can be accomodated. Two fuses are required.
Operation up to 240 volts is possible with no change in performance using the 220 volt
setting. Optimal operation requires 115 volts AC.
Maintenance
The Model DA924 is an auto calibrating converter requiring no periodic adjustments. The
unit's reliance on linear power supplies and discrete class A analog circuitry generates a
significant amount of heat (25 watts maximum). The temperature rise is no cause for
concern, but allowing for some air flow is always a benefit from a long term reliability
stand point.
