15-8
LatticeECP2/M sysCONFIG Usage Guide
JTAG control the dedicated programming pins INITN, DONE, and CCLK have no meaning. This is because a
boundary scan cell will control each pin, per the IEEE standard, rather than normal internal logic. While the
LatticeECP2/M is under JTAG control the PROGRAMN pin will be ignored.
These pins are powered by V
CCJ
.
TDO
The Test Data Output pin is used to shift out serial test instructions and data. When TDO is not being driven by the
internal circuitry, the pin will be in a high impedance state. This pin should be wired to TDO of the JTAG connector,
or to TDI of a downstream device in a JTAG chain. An internal pull-up resistor on the TDO pin is provided. The
internal resistor is pulled up to V
CCJ
.
TDI
The Test Data Input pin is used to shift in serial test instructions and data. This pin should be wired to TDI of the
JTAG connector, or to TDO of an upstream device in a JTAG chain. An internal pull-up resistor on the TDI pin is
provided. The internal resistor is pulled up to V
CCJ
.
TMS
The Test Mode Select pin controls test operations on the TAP controller. On the falling edge of TCK, depending on
the state of TMS, a transition will be made in the TAP controller state machine. An internal pull-up resistor on the
TMS pin is provided. The internal resistor is pulled up to V
CCJ
.
TCK
The test clock pin, TCK, provides the clock to run the TAP controller state machine, which loads and unloads the
JTAG data and instruction registers. TCK can be stopped in either the high or low state and can be clocked at fre-
quencies up to that indicated in the device data sheet. The TCK pin supports hysteresis; the typical hysteresis is
approximately 100mV when V
CCJ
= 3.3V. The TCK pin does not have a pull-up. A pull-down resistor between TCK
and ground on the PCB of 4.7 K is recommended to avoid inadvertent clocking of the TAP controller as V
CC
ramps
up.
When downloading an encrypted bitstream file to the LatticeECP2/M S-Series devices, the user must adhere to the
appropriate conditions for the TCK signal. These conditions are shown in TN1109,
Optional TRST
Test Reset, TRST, in not supported on the LatticeECP2/M.
V
CCJ
Having a separate JTAG V
CC
(V
CCJ
) pin lets the user apply a voltage level to the JTAG port that is independent
from the rest of the device. Valid voltage levels are 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V, but the voltage used must
match the other voltages in the JTAG chain. V
CCJ
must be connected even if JTAG is not used.
In-System Programming Design Guidelines for ispJTAG Devices
for further information.
Configuration and JTAG Pin Physical Description
All of the sysCONFIG dedicated and dual-purpose pins are part of Bank 8. Bank 8 V
CCIO
determines the output
voltage level of these pins, input thresholds are determined by the I/O Type selected in the ispLEVER Design Plan-
ner (default is 3.3V LVCMOS) or Diamond Spreadsheet View.
JTAG voltage levels and thresholds are determined by the V
CCJ
pin, allowing the LatticeECP2/M to accommodate
JTAG chain voltages from 1.2V to 3.3V.
Configuration Modes
The LatticeECP2/M devices support many different configuration modes, utilizing either serial or parallel data
paths. On power-up, when a JTAG Refresh instruction is issued, or when the PROGRAMN pin is toggled, the
CFG[2:0] pins are sampled to determine the configuration mode. See Table 15-3 above for a list of available config-
uration modes.