Certus-NX Versa Evaluation Board Demo
User Guide
© 2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
22
FPGA-UG-02133-1.1
7.
Regenerating the .bit File and Reprogramming the Board
You can implement changes in design using the HDL source flow.
To regenerate the bit file following modifications to the source code:
1.
Open the Lattice Radiant design software.
2.
Click Open Project.
3.
In the Open Project dialog box, navigate to and select the LFD2NX40_PCIe_Basic_Demo.rdf file located in this kit
at <kit-location>\Lattice_certus_nx_pcie_basic_demo\Hardware\CertusNXBoard_PCIeBasicDemo\
Implementation\LFD2NX40_PCIe_Basic_Demo\LFD2NX40_PCIe_Basic_Demo.rdf
4.
Click Open. All the Verilog HDL files are imported into the project.
5.
In Project > Project Properties, verify your settings as shown in
Figure 7.1. Proper Project Properties Configuration
6.
Once your project loads, click Task Detail View. This shows a list of actions that Lattice Radiant will perform to build
the .bit file.
7.
Select the files and reports that you want to generate.
Note: The options needed to regenerate the .bit file are selected by default.
8.
After selecting your preferred reports, click Run All.
This creates a .bit file with your project's current name in the imp1 folder. Assuming you left the directory structure
of this original project unchanged, the file becomes available in the following location:
<kit_location>\Lattice_certus_nx_pcie_basic_demo\Hardware\CertusNXBoard_PCIeBasicDemo\Implementation\LF
D2NX40_PCIe_Basic_Demo/<your_file>.bit
9.
Once the file is generated, click Programmer.
The process to reprogram the non-volatile memory onboard the FPGA is completed, similar to the initial install. This
secondary pass, however, does not require you to create a new programmer project.
