19
ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
Edge Clock Dividers (CLKDIVF)
There are four edge clock dividers available in the ECP5 and ECP5-5G device, two per side of the device. The
clock divider provides a single divided output with available divide values of 2 or 3.5. The inputs to the clock divid-
ers are the edge clocks, PLL outputs and Primary Clock Input pins. The outputs of the clock divider drive the pri-
mary clock network and are mainly used for DDR I/O domain crossing.
CLKDIVF Component Definition
The CLKDI
V
F component can be instantiated in the source code of a design as defined in this section. Figure 17,
Table 9, and Table 10 define the CLKDI
V
F component.
V
erilog and
V
HDL instantiations are included.
Figure 17. CLKDIVF Component Symbol
Table 9. CLKDIVF Component Port Definition
Table 10. CLKDIVF Component Attribute Definition
The ALIGNWD input is intended for use with high-speed data interfaces such as DDR or 7:1 L
V
DS
V
ideo.
CLKDIVF Usage in VHDL
Component Instantiation
Library lattice;
use lattice.components.all;
Component and Attribute Declaration
component CLKDIVF
Generic (DIV : string;
GSR : string);
Port (RST : in STD_LOGIC;
CLKI : in STD_LOGIC;
ALIGNWD : in STD_LOGIC;
CDIVX : out STD_LOGIC);
end component;
Port Name
I/O
Description
CLKI
I
Clock Input.
RST
I
Reset input – Active High, Asynchronously forces all
outputs low.
—
RST = 0 Clock outputs are active
—
RST = 1 Clock outputs are OFF
ALIGNWD
I
Signal is used for word alignment.
When enabled it slips the output one
cycle relative to the input clock.
CDI
V
X
O
Divide by 2 or 3.5 Output Port
Name
Description
Value
Default
GSR
Enable or Disable Global Reset
Signal to Component
ENABLED, DISABLED
DISABLED
DI
V
CLK Divider
V
alue
2.0 or 3.5
2.0
CLKDIVF
CLKI
RST
ALIG
NW
D
CDIVX
