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MachXO5-NX Development Board
Preliminary Evaluation Board User Guide

© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at

www.latticesemi.com/legal

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

30

FPGA-EB-02052-0.90

AK_SCL/AK_SDA with SCL1/SDA1 and SCL2/SDA2, or add bridge resistors according to Table 8.14

to connect all of them

to SCL0/SDA0 for bridge interconnections on board without involvement of FPGA. You also need to setup the design
with tri-state mode for outputting high with pull up resistors. If there is no pull up setup on the counterpart boards or
internal GPIOs of FPGA, you can add JP12 and JP13 to leverage the R33 and R34 for pulling up bridge SCL0/SDA0 to
selectable VCCIO2. Take care that the DPHY0_SCL/DPHY0_SDA are special case. They need dedicate pull up resistors
R233/R234 due to they are supported from 1.8 V I/O Bank 9. Also, R233/R234 can be used to pull up SCL0/SDA0 by
adding R229/R228 when Bank 7 is selected to support 1.8 V for FX12 header I

2

C control. At this time, JP12 and JP13

should be removed and R224/R225 or R226/R227 should be added to leverage the 1.8 V pull up for I/O Bank 7.

Table 8.14. I

2

C Connections

Extend header

MachXO5-25 Bank

MachXO5-25 Ball

Location for JTAG

Net Name

Bridge Resistor to

SCL0/SDA0

Versa Header

(J9)

0

D5

EXPCON_IO13

R35 (DNI)

B5

EXPCON_IO15

R37 (DNI)

Aardvark Header

(J7)

3

M19

AK_SCL

R231 (DNI)

M20

AK_SDA

R230 (DNI)

Arduino Header

(J2)

3

N19

AR_SCL

R45 (DNI)

N18

AR_SDA

R44 (DNI)

FX12 Headers

(U4/U5)

7

R5

SCL1

R224 (DNI)

R4

SDA1

R225 (DNI)

FX12 Headers

(U4/U5)

7

R7

SCL2

R226 (DNI)

R6

SDA2

R227 (DNI)

Raspberry Pi Header (J6)

8

K1

RASP_ID_SC

R85 (DNI)

K2

RASP_ID_SD

R87 (DNI)

Raspberry Pi Header (J6)

8

L7

RASP_IO03

R96 (DNI)

L8

RASP_IO02

R84 (DNI)

Camera Header

(J27)

9

H6

DPHY0_SCL

R229 (DNI)

H5

DPHY0_SDA

R228 (DNI)

8.9.

ADC and Potentiometer

There are two dedicate ADC input pairs for MachXO5-25. This board provides multiple application options. For default population,
one pair of ADC0 is used to measure the core VCC voltage drop through a 10 mΩ resistor R112. Therefore, the core VCC current is
calculable, as shown in

. Positive input of another pair ADC1 is connected to a 10 kΩ Trimmer Potentiometers (POT1)

which provides voltage variation from 0 V to selectable VCCIO4, as shown in

. The negative input of ADC1 is grounded

through 1 kΩ resistor.

Figure 8.3. Circuit Design for ADC0

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Содержание MachXO5-NX Development Kit

Страница 1: ...MachXO5 NX Development Board Preliminary Evaluation Board User Guide FPGA EB 02052 0 90 May 2022...

Страница 2: ...ded AS IS with all faults and associated risk the responsibility entirely of the Buyer Buyer shall not rely on any data and performance specifications or parameters provided herein Products sold by La...

Страница 3: ...5 4 2 Soft UART User Interface 15 5 MachXO5 25 Clock Sources 17 6 SGMII Ethernet Connections 18 7 HyperRAM 20 8 Headers and Test Connections 21 8 1 Versa Headers 21 8 2 Arduino Board GPIO Headers 23 8...

Страница 4: ...face 13 Figure 3 4 JTAG Test Header 13 Figure 3 5 I2 C Programming Mode 14 Figure 4 1 JTAG UART User Interfacing 15 Figure 5 1 Onboard Clock Resources 17 Figure 8 1 MIPI Camera Sensor Interface 28 Fig...

Страница 5: ...ock Options 17 Table 6 1 SGMII Ethernet PHY Connections 18 Table 7 1 HyperRAM Pin Mapping 20 Table 8 1 Versa J8 Header Pin Connections 21 Table 8 2 Versa J9 Header Pin Connections 22 Table 8 3 Arduino...

Страница 6: ...marks of their respective holders The specifications and information herein are subject to change without notice 6 FPGA EB 02052 0 90 Acronyms in This Document A list of acronyms used in this document...

Страница 7: ...the following MachXO5 NX Development Board pre loaded with the demo design 12 V AC DC Power adapter Mini USB cable Quick Start Guide The contents of this user guide include top level functional descri...

Страница 8: ...Check Appendix D for the board revision information HyperRAM upto 166MHz x16 bits Versa Headers bridge with Lattice ASC Demo Board to support L ASC10 General Purpose Input Output GPIO interface with P...

Страница 9: ...lopment Board features the MachXO5 25 in a 400 ball caBGA package This device offers a variety of features and programmability that enhances Secure Control PLD functionality with Multiple Boot capabil...

Страница 10: ...3V 3 3V VCCIO8 U3 J23 3 3V 3 3V VCCIO7 U3 J22 3 3V 1 8V VCCIO4 U3 J29 1 2V 2 5V VCCIO6 U3 J21 1 2V 1 8V VCCIO5 U3 J20 1 8V 1 2V 5V VCCIO9 U3 1 8V VCCAUX VCCAUXA VCCAUX H VCCADC U3 1 8V FX12 Headers U4...

Страница 11: ...0 and VCCIO2 share the same three positions jumper J25 and short its Pin 1 and Pin 2 can bring the 3 3 V LDO output to both I O bank 0 and bank 2 For power consumption evaluation this board facilitate...

Страница 12: ...PC ensuring FTDI reset control jumper JP9 is not populated as default The software select option FTUSB 0 is dedicate for hard JTAG and FTUSB 1 is dedicate for hard I2 C which is mapping with port A a...

Страница 13: ...cifications and information herein are subject to change without notice FPGA EB 02052 0 90 13 output tri state mode avoiding multi drivers on those shared signals The JTAG connections between J1 and M...

Страница 14: ...B function on Config FTDI Port B and you can select the port FTUSB 1 on the programmer interface for the accessing from Config FTDI Port B to the MachXO5 25 dedicated I2 C download port Figure 3 2 tha...

Страница 15: ...JTAG and FTUSB 1 is targeted for UART that is mapped with port A and port B from hardware perspective Mini USB J19 USB FT2232H U18 Port A Port B MachXO5 NX U3 rst JP8 GND RS232_RX_TTL UTDI UTCK UTMS...

Страница 16: ...or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice 16 FPGA EB 02052 0 90 Table 4 2 Soft...

Страница 17: ...XPCON_OSC J11 J19 USB USB Clock Generator SMA Figure 5 1 Onboard Clock Resources You need take care that only 27 MHz and 125 MHz clocks are active in default after board power up Both 12 MHz clocks fr...

Страница 18: ...1 TD_M_D SGMII_MD3_P To RJ45 12 RBIAS Pull down to GND 13 VDDA1P8 SGMII_PHY_D1V8 1 8 V Power 14 XO SGMII_XO 25 MHz Crystal Output 15 XI SGMII_XI 25 MHz Crystal Input 16 MDC SGMII_MDIO_CLK U1 Optional...

Страница 19: ...demarks of their respective holders The specifications and information herein are subject to change without notice FPGA EB 02052 0 90 19 U7 Pin Number U7 Signal Name Net Name MachXO5 25 Ball Location...

Страница 20: ...ard Table 7 1 HyperRAM Pin Mapping Cypress HyperRAM in 24 Ball FBGA Connection for HyperRAM0 U6 Connection for HyperRAM1 U9 Symbol Name Ball Location Net Name MachXO5 25 Ball Location Net Name MachXO5...

Страница 21: ...ions 8 1 Versa Headers The board provides two headers J8 and J9 for expansion purpose Table 8 1 Versa J8 Header Pin Connections J8 Pin Number Net Name MachXO5 25 Ball Location 1 GND 2 NC 3 EXPCON_2V5...

Страница 22: ...ons J9 Pin Number Net Name MachXO5 25 Ball Location 1 HPE_RESOUT F5 2 GND 3 EXPCON_IO0 D3 4 EXPCON_IO1 E4 5 EXPCON_IO2 C3 6 EXPCON_IO3 C2 7 EXPCON_IO4 A4 8 EXPCON_IO5 E5 9 EXPCON_IO6 F6 10 EXPCON_IO7...

Страница 23: ...AR_AREF AREF PA03 L19 AR_AREF connection to AREF through R43 9 AR_SDA D20 PA22 SDA N18 Defaults to SDA function on Arduino ZERO Board It is optionally connected to SDA0 through R44 DNI 10 AR_SCL D21...

Страница 24: ...AR_AD3 D17 ADC3 PA04 M14 Defaults to ADC3 on Arduino ZERO Board 5 AR_AD4 D18 ADC4 PA05 M17 Defaults to ADC4 on Arduino ZERO Board 6 AR_AD5 D19 ADC5 PB02 M18 Defaults to ADC5 on Arduino ZERO Board 8 3...

Страница 25: ...N V10 38 PWR_5 0V 39 SDA1 R4 40 SCL1 R5 Notes Signal is optionally connected to power source through resistor DNI 12 V power needs external supply from pin 8 of J4 Table 8 8 FX12 U5 Header Pin Connect...

Страница 26: ...ough USB It allows you to interface a Windows Linux or Mac OS X PC through USB to a downstream embedded system environment and transfer serial messages using the I2 C and SPI protocols The MachXO5 NX...

Страница 27: ...4 RASP_IO08 P2 25 GND 26 RASP_IO07 P1 27 RASP_ID_SD K2 28 RASP_ID_SC K1 29 RASP_IO05 N3 30 GND 31 RASP_IO06 N4 32 RASP_IO12 P3 33 RASP_IO13 P4 34 GND 35 RASP_IO19 P5 36 RASP_IO16 M5 37 RASP_IO26 P6 38...

Страница 28: ...lopment Board support MIPI Camera sensor input with soft D PHY Figure 8 1 shows the block diagram of the MIPI Camera Sensor interface on the board The data path interface between the camera sensor mod...

Страница 29: ...13 10 GND 11 DPHY0_DN0 T13 12 DPHY0_DP0 U13 13 GND 14 DPHY0_DN2 U14 15 DPHY0_DP2 V13 16 GND 17 GND 18 VDD2V8 19 NC 20 DPHY0_CLK K7 21 DPHY0_FSYNC K6 22 DPHY0_SDA H5 23 DPHY0_SCL H6 24 DPHY0_RST H7 25...

Страница 30: ...12 header I2 C control At this time JP12 and JP13 should be removed and R224 R225 or R226 R227 should be added to leverage the 1 8 V pull up for I O Bank 7 Table 8 14 I2 C Connections Extend header Ma...

Страница 31: ...8 5 To increase the voltage to ADCP1 rotate the POT counter clockwise Decreasing Wiper Voltage Wiper CW CCW Clockwise 1 2 3 Figure 8 5 Trimmer Wiper Description Optionally both ADC pairs are also rout...

Страница 32: ...ll other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice 32 FPGA EB 02052 0 90...

Страница 33: ...re connected to the four switches of SW1 as shown in the circuit design in Figure 9 1 The CTS side actuated DIP switches are connected to logic level 0 when in the ON position as shown in Figure 9 2 F...

Страница 34: ...o connect with EXPCON_IO20 which is connect to MANDATORY_RESET signal when mated with Lattice ASC Bridge Board Refer to ASC Bridge Board Evaluation Board User Guide FPGA EB 02025 for detailed informat...

Страница 35: ...com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA EB 02...

Страница 36: ...MachXO5 NX Development Board Radiant 3 11 or later version Radiant Programmer 3 11 or later version 11 Storage and Handling Static electricity can shorten the life span of electronic components Observ...

Страница 37: ...disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein ar...

Страница 38: ...6 Arduino Aardvark Headers BANK3 4 07 High Speed Headers BANK5 6 08 Raspberry Pi and LEDs BANK7 8 09 HyperRAM and ADC BANK9 10 POWER RAILS 11 POWER REGULATORS Date Size Schematic Rev o f Sheet Title L...

Страница 39: ...IOs 1 8V 3 3V 24 IOs 1 2V 1 8V 24 IOs 1 2V 1 8V MIPI I F Control Pg7 Pg8 LEDs VCCIO0 2 U3 100mA 3 3V Prototype Area Pg6 50mA 1 8V 100mA 2 5V VCCIO3 U3 100mA 1 8V VCCIO7 U3 100mA 3 3V 100mA 3 3V 100mA...

Страница 40: ...tor Applications Email techsupport Latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project 1 0 MachXO5 NX Development Board B 3 11 Thursday January 13 2022 A USB to Hard JTAG I F D9 Red C9...

Страница 41: ...Applications Email techsupport Latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project 1 0 MachXO5 NX Development Board B 4 10 Thursday January 13 2022 A USB to Soft JTAG I F BANK1 C140 10...

Страница 42: ...FTDI_SCL 3 FTDI_SDA 3 SCL0 3 6 8 9 SDA0 3 6 8 9 Date Size Schematic Rev o f Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev...

Страница 43: ...com Phone 503 268 8001 or 800 LATTICE Board Rev Project 1 0 MachXO5 NX Development Board B 6 11 Thursday January 13 2022 A Arduino Aardvark Headers BANK3 4 Date Size Schematic Rev o f Sheet Title Lat...

Страница 44: ...Project 1 0 MachXO5 NX Development Board C 7 11 Thursday January 13 2022 A High Speed Heads BANK5 6 D13 Red R38 2 2K DNI C146 100nF C181 1uF R56 100 DNI C175 1uF C158 1uF R54 100 DNI R49 100 DNI C18 1...

Страница 45: ...R1 9 MDIR0 9 MEN0 9 MEN1 9 Date Size Schematic Rev o f Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project 1 0 MachXO5...

Страница 46: ...oard Rev Project 1 0 MachXO5 NX Development Board B 9 11 Thursday January 13 2022 A HyperRAM and ADC BANK9 Date Size Schematic Rev o f Sheet Title Lattice Semiconductor Applications Email techsupport...

Страница 47: ...ct 1 0 MachXO5 NX Development Board B 10 11 Thursday January 13 2022 A POWER RAILS Date Size Schematic Rev o f Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Phone 50...

Страница 48: ...13 2022 A POWER REGULATORS Date Size Schematic Rev o f Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Phone 503 268 8001 or 800 LATTICE Board Rev Project 1 0 MachXO5...

Страница 49: ...C130 4 4 7uF C0603 885012106005 Wurth CAP CER 4 7UF 6 3V X5R 0603 3 C2 C4 C6 C7 C10 C11 C12 C13 C14 C17 C20 C21 C22 C23 C24 C25 C26 C27 C29 C30 C34 C62 C81 C85 C86 C87 C90 C92 C94 C96 C98 C99 C100 C1...

Страница 50: ...17 C118 C158 C159 C160 C161 C167 C168 C173 C175 C179 C181 C185 13 1uF C0603 CL10A105KO8 NNNC Samsung CAP CER 1UF 16V X5R 0603 13 C119 C120 2 3 3nF C0201 GRM033R71A3 32JA01D Murata CAP CER 3300PF 10V X...

Страница 51: ...HEADER VERT 6POS 2 54MM DNI 26 J6 1 Receptac le 20X2 HDR254 2X20_soc ket PPTC202LFBN RC Sullins CONN HEADER FEM 40POS 1 DL TIN DNI 27 J7 1 HEADER 5X2 HDR254 2X5_SHR OUDED 30310 6002HB 3M CONN HEADER 1...

Страница 52: ...T 1R5M SPM6530 T 2R2M SPM6530T 1R5M100 TDK FIXED IND 1 5UH 11A 10 67MOHM SM 41 L10 1 SPM653 0T 3R3M SPM6530 T 2R2M SPM6530T 3R3M HZ TDK FIXED IND 3 3UH 6 8A 29 7MOHM SM 42 POT1 1 3314G 1 103E sot23 33...

Страница 53: ...R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 16 100 R0201 DNI 55 R65 R66 2 2 49K R0603 RT0603DRE072 K49L yageo RES SMD 2 49KOHM 0 5 1 10W 0603 56 R70 R71 R72 R109 R11 0 R144 R162 R163 R17...

Страница 54: ...TP17 TP18 TP19 TP20 TP21 20 T POINT R TP DNI 70 U1 U18 2 FT2232H L tqfp64_0p 5_12p2x1 2p2_h1p6 FT2232HL TRAY FTDI IC USB HS DUAL UART FIFO 64 LQFP 71 U2 U19 2 93LC56C I SN so8_50_2 44 93LC56C I SN Mic...

Страница 55: ...Description Assembly 81 U15 1 RP115H1 81D SOT 89 5 SOT89 5 RP115H181D T1 FE RICOH IC REG LINEAR 1 8V 1A SOT89 5 82 U16 1 RP115H1 21D SOT 89 5 SOT89 5 RP115H121D T1 FE RICOH IC REG LINEAR 1 2V 1A SOT8...

Страница 56: ...itch Connections ldc_set_location site T1 get_ports DIPSW 0 ldc_set_location site T2 get_ports DIPSW 1 ldc_set_location site T3 get_ports DIPSW 2 ldc_set_location site T4 get_ports DIPSW 3 Push Button...

Страница 57: ...G7 get_ports PMOD0_1 ldc_set_location site G9 get_ports PMOD0_2 ldc_set_location site G8 get_ports PMOD0_3 ldc_set_location site H8 get_ports PMOD0_4 ldc_set_location site F7 get_ports PMOD0_5 ldc_set...

Страница 58: ..._set_location site L4 get_ports RASP_IO27 ldc_set_location site K1 get_ports RASP_ID_SC ldc_set_location site K2 get_ports RASP_ID_SD VERSA HEADER Connections ldc_set_location site D3 get_ports EXPCON...

Страница 59: ...N_CLKOUT ldc_set_location site F5 get_ports HPE_RESOUT ldc_set_location site D8 get_ports HPE_CARDSEL Aardvark Header Connections ldc_set_location site M19 get_ports AK_SCL ldc_set_location site M20 g...

Страница 60: ...s The specifications and information herein are subject to change without notice 60 FPGA EB 02052 0 90 Appendix D MachXO5 NX Development Board Revision Information MachXO5 NX Development Board Working...

Страница 61: ...tticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice...

Страница 62: ...tents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information...

Страница 63: ......

Страница 64: ...www latticesemi com...

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