MachXO3-9400 Development Board
Evaluation Board User Guide
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
www.latticesemi.com/legal
.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
42
FPGA-EB-02004-1.0
Figure A.6. CrossLink Headers (BANK2)
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
NOTE : PLACE ALL THE TERMINATION
RESISTORS ON TOP SIDE AND CLOSE
TO THE U3
LVDS RX TERMINATION RESISTORS
Note :
1) Match length within pair as well as other pairs with +/- 5% tolerence
2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals
3)All the power rails should be capable of carrying 1A current
R
X
C
o
n
n
e
c
t
o
r
2
Note : Speed of the bus, < 2.5ps skew for pairs and
across the bus, traces should be 100 Ohms
Trace match LVDSI* pins between P and N channels as
well as individual pairs.
R
X
C
o
n
n
e
c
t
o
r
1
NOTE : 0 OHM RESISTOR SHUOULD BE PLACED
NEAR U3
SPI FLASH
AARDVARK
Connector
AARDVARK
SPI FLASH
CrossLink Headers
NOTE : 0 OHM RESISTOR SHUOULD BE PLACED
NEAR U3
+12V
+12V
VCC1_8FT
+12V
+3.3V
VBUS_5V
+12V
+3.3V
VBUS_5V
VCC1_8FT
+12V
+12V
VCCIO2
VBUS_5V
VCCIO2
+3.3V VCC1_8FT
VBUS_5V
+3.3V VCC1_8FT
VBUS_5V
SDA0
[3,4,5,6,7]
SCL0
[3,4,5,6,7]
SCL0
[3,4,5,6,7]
SDA0
[3,4,5,6,7]
AR_SS_IO10
[5]
AR_MISO_IO12
[5]
AR_SCK_IO13
[5]
AR_MOSI_IO11 [5]
SISPI
[7]
MCLK
[7]
CSSPIN
[7]
SPISO
[7]
SN
[7]
JP2_SCL
[3]
JP2_SDA
[3]
Date:
Size
Schematic Rev
of
Sheet
Title
Lattice Semiconductor Applications
http://www.latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
4.0
MachXO3-9400-Dev-Brd
C
6
10
Monday, May 22, 2017
B
CrossLink Headers (BANK2)
Date:
Size
Schematic Rev
of
Sheet
Title
Lattice Semiconductor Applications
http://www.latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
4.0
MachXO3-9400-Dev-Brd
C
6
10
Monday, May 22, 2017
B
CrossLink Headers (BANK2)
Date:
Size
Schematic Rev
of
Sheet
Title
Lattice Semiconductor Applications
http://www.latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
4.0
MachXO3-9400-Dev-Brd
C
6
10
Monday, May 22, 2017
B
CrossLink Headers (BANK2)
R272
0
DNI
R81
0
DNI
R74
250
U4
Hirose - FX12 - 40 Pos
DNI
CH0_DCK_P
1
CH0_DCK_N
2
GND
3
CH0_DATA0_P
4
CH0_DATA0_N
5
GND
6
CH0_DATA2_P
7
CH0_DATA2_N
8
GND
9
SN
10
SCLK
11
PWR_12V
12
SDA1
13
SCL1
14
GND
15
CH2_DATA0_P
16
CH2_DATA0_N
17
GND
18
CH2_DCK_P
19
CH2_DCK_N
20
PWR_12-0V
21
RESETN
22
PWR_5-0V
23
CH0_DATA1_P
24
CH0_DATA1_N
25
PWR_3-3V
26
CH0_DATA3_P
27
CH0_DATA3_N
28
PWR_1-8V
29
MOSI
30
MISO
31
PWR_1-8V
32
GND
33
GND
34
PWR_3-3V
35
CH2_DATA1_P
36
CH2_DATA1_N
37
PWR_5-0V
38
SDA
39
SCL
40
Shield1
41
Shield2
42
Shield3
43
Shield4
44
Shield5
45
Shield6
46
BANK 2
XO3L_10K_484CABGA
U3B
PB5A
AA2
PB5B
AB2
PB5C
V6
PB5D
U6
PB7A_CSSPIN
AA3
PB7B
AB3
PB7C
Y4
PB7D
W5
PB8C
U7
PB8D
T8
PB8A
AA4
PB8B
AB4
PB10A
AA5
PB10B
AB5
PB10C
Y5
PB10D
Y6
PB13C
V8
PB13D
U8
PB16A_MCLK/CCLK
T9
PB16B_SO/SPISO
U9
PB18A
AA8
PB18B
AB8
PB21A
V10
PB21B
W10
PB22A_PCLKT2_0
AA10
PB22B_PCLKC2_0
AB10
PB24A
AA11
PB24B
AB11
PB24C
V11
PB24D
Y11
PB29A_PCLKT2_1
AB12
PB29B_PCLKC2_1
AA12
PB30A
AB13
PB30B
AA13
PB33A
AB14
PB33B
AA14
PB43A
AB19
PB43B
AA19
PB44A
AB20
PB44B
AA20
PB46A_SN
AB21
PB46B_SI/SISPI
AA21
PB35A
AB15
PB35B
AA15
PB11A
AA6
PB11B
AB6
PB11C
W6
PB11D
V7
PB13A
AA7
PB13B
AB7
PB16C
V9
PB16D
W8
PB18C
Y8
PB18D
W9
PB19A
AA9
PB19B
AB9
PB19C
T10
PB19D
U10
PB22C
T11
PB22D
U11
PB27A
Y12
PB27B
T12
PB27C
U12
PB27D
V12
PB29C
V13
PB29D
U13
PB30C
Y13
PB30D
W13
PB33C
Y14
PB33D
W14
PB32A
T13
PB32B
T14
PB32C
U14
PB32D
V14
PB35C
Y15
PB35D
W15
PB38A
AB16
PB38B
AA16
PB38C
V15
PB38D
U15
PB40A
AB17
PB40B
AA17
PB40C
Y17
PB40D
V16
PB41A
AB18
PB41B
AA18
PB41C
Y18
PB41D
W17
PB43C
T15
PB43D
U16
PB44C
Y19
PB44D
W18
PB46C
V17
PB46D
T16
PB21C
Y9
PB21D
Y10
R64
100
DNI
R62
100
DNI
C23
0.1uF
R60
100
DNI
C27
0.1uF
C22
0.1uF
R79
0
DNI
R157
0
DNI
C28
100nF
10V
R155
0
DNI
R69
10K
R71
0
DNI
R72
0
R68
910
R54
100
DNI
R152
0
DNI
JP2
HEADER 5X2
DNI
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
R80
10K
R59
100
DNI
R77
0
DNI
R50
100
DNI
C26
0.1uF
R161
0
DNI
C25
0.1uF
R271
0
DNI
R49
100
DNI
R67
0
DNI
JP8
JUMPER
1
2
R61
100
DNI
R154
0
DNI
R58
100
DNI
R160
0
C24
0.1uF
R53
100
DNI
R56
100
DNI
C20
0.1uF
R73
0
R273
0
DNI
C21
0.1uF
U6
S25FL116K0XMFI043
CS
1
SDI
5
SCK
6
WP
3
HOLD
7
V
C
C
8
G
N
D
4
SDO
2
U5
Hirose - FX12 - 40 Pos
DNI
CH1_DCK_P
1
CH1_DCK_N
2
GND
3
CH1_DATA0_P
4
CH1_DATA0_N
5
GND
6
CH1_DATA2_P
7
CH1_DATA2_N
8
GND
9
SN
10
SCLK
11
PWR_12_0V
12
SDA1
13
SCL1
14
GND
15
CH3_DATA0_P
16
CH3_DATA0_N
17
GND
18
CH3_DCK_P
19
CH3_DCK_N
20
PWR_12V
21
RESETN
22
PWR_5-0V
23
CH1_DATA1_P
24
CH1_DATA1_N
25
PWR_3-3V
26
CH1_DATA3_P
27
CH1_DATA3_N
28
PWR_1-8V
29
MOSI
30
MISO
31
PWR_1-8V
32
GND
33
GND
34
PWR_3-3V
35
CH3_DATA1_P
36
CH3_DATA1_N
37
PWR_5-0V
38
SDA
39
SCL
40
Shield1
41
Shield2
42
Shield3
43
Shield4
44
Shield5
45
Shield6
46
R83
0
DNI
R156
0
DNI
R76
0
DNI
R274
0
DNI
R55
100
DNI
R65
10K
R51
100
DNI
R52
100
DNI
R78
0
DNI
R153
0
DNI
R66
10K
R82
0
DNI
R63
100
DNI
R57
100
DNI
R70
0
DNI
CH0_DCK_P
CH0_DCK_N
CH0_DATA0_N
CH0_DATA0_P
CH0_DATA1_P
CH0_DATA1_N
CH2_DATA1_N
CH2_DATA1_P
CH1_DCK_P
CH1_DCK_N
CH0_DATA3_P
CH0_DATA3_N
CH0_DATA2_N
CH0_DATA2_P
CH1_DATA0_N
CH1_DATA1_P
CH1_DATA0_P
CH1_DATA1_N
CH1_DATA2_N
CH1_DATA2_P
CH2_DATA0_P
CH2_DATA0_N
CH2_DCK_N
CH2_DCK_P
CH1_DATA3_N
CH1_DATA3_P
CH3_DATA1_N
CH3_DATA1_P
CH3_DCK_N
CH3_DCK_P
CH3_DATA0_N
CH3_DATA0_P
FX_MOSI
FX_SN
FX_SCLK
FX_MISO
CH1_DCK_P
CH1_DCK_N
CH1_DATA0_P
CH3_DATA0_N
CH1_DATA0_N
CH1_DATA2_P
RESETN
CH1_DATA2_N
CH3_DCK_N
CH1_DATA3_N
CH1_DATA3_P
CH1_DATA1_N
CH3_DATA0_P
CH1_DATA1_P
CH3_DATA1_N
CH3_DATA1_P
CH3_DCK_P
CH0_DATA2_P
CH0_DATA1_P
CH0_DCK_P
CH0_DCK_N
CH0_DATA0_P
CH0_DATA0_N
CH0_DATA2_N
CH2_DATA0_P
CH2_DATA0_N
CH2_DCK_P
CH2_DCK_N
CH0_DATA1_N
CH0_DATA3_P
CH0_DATA3_N
CH2_DATA1_P
CH2_DATA1_N
RESETN
CH3_DATA0_N
CH0_DCK_P
AR_SS_IO10
CH1_DCK_P
CH0_DCK_N
CH3_DATA0_P
MCLK
SDA1
SCL2
SCL1
SDA2
SPISO
CSSPIN
SISPI
CH1_DCK_N
CSSPIN
SDO
SPISO
MCLK
SS
SISPI
JP2_SDA
JP2_SCL
+5V_SPI
+5V_I2C
SN
RESETN
SDA2
SCL2
SDA1
SCL1
SCL2
SDA2
SCL1
SDA1
MCLK
SCK
SPISO
SISPI
SDI
CS#
SS
CSSPIN
SN
WP#
HOLD#
WP#
HOLD#
CH0_DATA2_P
CH0_DATA2_N
CH2_DATA0_N
CH2_DATA0_P
CH2_DCK_P
CH2_DCK_N
CH0_DATA3_N
CH0_DATA3_P
CH2_DATA1_N
CH2_DATA1_P
CH1_DATA1_N
CH1_DATA1_P
CH1_DATA3_P
CH1_DATA3_N
CH1_DATA0_P
CH1_DATA0_N
CH1_DATA2_P
CH1_DATA2_N
CH3_DCK_N
CH3_DCK_P
CH3_DATA1_P
CH3_DATA1_N
CH0_DATA1_N
CH0_DATA1_P
CH0_DATA0_N
CH0_DATA0_P
PWR_3-3V_L
PWR_1-8V_L
PWR_5-0V_R
PWR_3-3V_R
PWR_1-8V_R
FX_SCLK
FX_MOSI
SISPI
MCLK
FX_MISO
FX_SN
CSSPIN
SPISO
FX_MOSI
FX_MISO
FX_SN
FX_SCLK
PWR_5-0V_L