Lattice Semiconductor LFSC80E-P4-EV, Руководство пользователя

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LatticeSC PCI Express x4 Evaluation Board
Lattice Semiconductor User’s Guide
High Speed Test Point
DP1
(see Appendix A, Figure 12)
General-purpose FPGA pins are available via a differential test pad. These connections allow a high-impedance
probe to measure the performance of a coupled- differential output buffer pair.
DDR2 Memory
U18
(see Appendix A, Figure 11)
The LatticeSC Evaluation Board is equipped with an 84-BGA DDR2 SDRAM memory device such as a Micron
MT47H16M16BG-3 device. The DDR2 memory interface includes a 16-bit wide device. The evaluation board
includes termination of address and command signals. It includes all power and external components needed to
demonstrate the memory controller of the LatticeSC device.
Ordering Information
Description Ordering Part Number
China RoHS Environment-Friendly
Use Period (EFUP)
LatticeSC PCI Express x4 Evaluation Board LFSC80E-P4-EV 10
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
Revision History
Date Version Change Summary
July 2007 01.0 Initial release.
December 2007 01.1 Updated FPGA Clock Management text section.
September 2009 01.2 Updated On-Board Flash Memory text section.
© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at
www.latticesemi.com/legal . All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
J49 URC_PLLC PR16B/URC_PLLT_IN_A G5 50-ohm Ground Termination R167
J50 PCLKT3_1 PR50C U6 50-ohm Ground Termination R168
J51 PCLKC3_1 PR50D V6 50-ohm Ground Termination R169
Table 12. FPGA I/O Test SMA Connectors (Continued)
SMA
Designation Name LFSC80 Signal
1152
BGA
Termination Description
Termination
Resistor(s)