8
LatticeSC PCI Express x4 Evaluation Board
Lattice Semiconductor
User’s Guide
MODE [3:0]
(see Appendix A, Figure 7)
The FPGA MODE pins are set on the board for a particular programming mode via the SW6 DIP switch. JTAG pro-
gramming is independent of the MODE pins and is always available to the user. Pushing in (depressing) the switch
is ON and sets the value to 0.
LatticeSC devices support many configuration modes. Listed below are the configuration modes supported on this
board. The modes are either directly supported or emulated using the CPLD on board.
Table 5. Configuration Mode Selections
MODE3 SW6-4
MODE2 SW6-3
MODE1 SW6-2
MODE0 SW6-1
Configuration Mode
0 (ON)
1 (OFF)
0 (ON)
1 (OFF)
SPI Flash
1 (OFF)
0 (ON)
0 (ON)
0 (ON)
Master Serial
1 (OFF)
1 (OFF)
1 (OFF)
1 (OFF)
Slave Serial
1 (OFF)
1 (OFF)
0 (ON)
0 (ON)
Master Parallel
0 (ON)
1 (OFF)
1 (OFF)
0 (ON)
Master Byte
1 (OFF)
0 (ON)
0 (ON)
1 (OFF)
Slave Parallel
X (don’t care)
X (don’t care)
X (don’t care)
X (don’t care)
ispJTAG
Bank1 VCCIO
(see Appendix A, Figure 8)
VCCIO1 can be selected on the board to be either 3.3V or 2.5V using J107.
A jumper shunt placed between pin 1 and pin 2 will connect 2.5V. A jumper shunt between pin 2 and pin 3 will con-
nect 3.3V. The user must pay attention to the design and select the correct supply for VCCIO1.
On-Board Flash Memory
(see Appendix A, Figure 7)
Three memory devices (U3 and U22) are on board for non-volatile configuration memory storage. SW3 is used to
control writing and reading from the memory. U3 is an 8M, 8-pin SOIC Flash device and U22 is a 64M, 16-pin
TSSOP Flash device. U22 is located on the bottom side (secondary) of the PCB.
Refer to TN1100,
SPI Serial Flash Programming Using ispJTAG in LatticeSC Devices
for recommended proce-
dures and software usage.
To use both SPI Flash devices to program the LatticeSC device, the user must write to the Flash devices individu-
ally. This is accomplished by setting SW3 accordingly. Writing to Flash #1 (U22), close 3 and 5 switch positions
(ON) and open all others.
Writing to Flash #2 (U3), close 2 and 4 switch positions (ON) and open all others.
For reading from the Flash devices individually, use the same switch settings as described for writing. For reading
from both Flash devices in a cascading format, close switch positions (1, 3, 4, 5, 8).
FPGA Clock Management
(see Appendix A, Figure 14)
The evaluation board includes various features for generating and managing on-board clocks. The clocks are gen-
erated from either input provided from SMAs (see Table 6) or from crystal oscillators (Y1 and Y3). Y1 is socketed
for interchangeability and Y3 is a 312.5MHz surface-mount with an enable/disable jumper (J102). Y4 and Y5 also
can be selected using J108 to disable Y5.
