18
LatticeXP2 Standard
Lattice Semiconductor
Evaluation Board User’s Guide
Figure 5. LatticeXP2 Power and Configuration
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
X
P
2B
an
k
2
_[
0.
.4
5]
X
P
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an
k
3
_[
0.
.4
3]
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P
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an
k
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0.
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1]
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5]
X
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7]
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P
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k
7
_[
0.
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XP2
_
J
T
A
G
[0
..3
]
XP2
_
J
T
A
G
1
XP2
_
J
T
A
G
2
XP2
_
J
T
A
G
3
XP2
_
J
T
A
G
0
VC
C
IO
1
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P
2_C
F
G
[0
..
10]
XP2
_
C
F
G
0
XP2
_
C
F
G
2
VC
C
IO
[0
..
7
]
VC
C
IO
3
VC
C
IO
0
VC
C
IO
2
VC
C
IO
7
VC
C
IO
4
VC
C
IO
5
VC
C
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6
X
P
2B
an
k
2
_[
0.
.4
5]
X
P
2B
an
k
3
_[
0.
.4
5]
X
P
2B
an
k
0
_[
0.
.5
1]
X
P
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k
1
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0.
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5]
X
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k
5
_[
0.
.5
2]
X
P
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an
k
4
_[
0.
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7]
X
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k
6
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0.
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5]
X
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k
7
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0.
.4
5]
VC
C
_
AU
X
VC
C
_
C
O
R
E
XP2
_
J
T
A
G
[0
..3
]
VC
C
_
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AG
VC
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IO
[0
..
7
]
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P
2_C
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[0.
.1
0]
Ti
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iz
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Do
c
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o
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Page 3
Page 4
H1
X
P
2_B
A
N
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0_3
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P
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k1
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0.
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5]
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2B
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k0
_[
0.
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1]
X
P
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k2
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0.
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5]
X
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k3
_[
0.
.4
5]
H3
X
P
2_B
A
N
K
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n
k4
_
[0
..
3
7
]
XP2
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k5
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[0
..
5
2
]
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k6
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5]
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0.
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2
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3
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5
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0
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D
K3
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D
L10
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D
L11
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D
L12
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D
L13
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1
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2
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2
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2
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2
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5
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2
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9
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3
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3
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3
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4
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8
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4
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6
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5
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6
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6
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