10
LatticeXP2 Standard
Lattice Semiconductor
Evaluation Board User’s Guide
Figure 3. Oscillator Positions
The output from the oscillator is routed to two series resistors. One of the series resistors is connected to a primary
clock input pin. The other resistor is connected to a PLL input pin. It is important to mention that DIP socket pin 8 is
shorted to pin 11, so it is not possible to input two different clock frequencies from the socket. In order to provide a
frequency on the primary clock input that is different from the PLL clock input it is necessary to remove one of the
two series termination resistors, and add a temporary modification to inject an electrically isolated clock signal.
Differential/50 Ohm Input/Output
The LatticeXP2 Standard Evaluation Board provides connections to differential I/O pins. The circuit board traces for
these connections are nominally 50-ohm impedance. Some of the differential I/O pins are inputs to primary or PLL
clock drivers. If the built-in oscillator in socket XU1 does not provide the right kind of input clock the SMA connec-
tors listed in Table 9 can be used to provide additional reference clock frequencies.
Table 9. Differential/50 Ohm Trace Pin Assignments
Power Supplies and Supply Control
The LatticeXP2 Standard Evaluation Board operates from a 5V DC input voltage. The input voltage is supplied via
J9, a coaxial DC input jack. The following components operate using the 5V input:
• ispPAC-POWR607 Power Manager
• Bellnix DC/DC converters
Connector Pair
LatticeXP2 I/O
Clock Input
J1
P1
N
J2
R1
N
J3
Physical connection
T1
Y (P)
Silkscreen text
W4
J4
Physical connection
U1
Y (N)
Silkscreen text
Y5
J6
P2
N
J10
P3
N
J7
T2 (3) / R2 (4)
N
J8
Physical connection Y5 (3) / W4 (4)
N
Silkscreen text
U1 (3) / T1 (4)
J24
J22
Y (P)
J25
K22
Y (N)
J26
K21
Y (P)
J27
L21
Y (N)
Full-Size Placement
Half-Size Placement
Pin 1
OSC
OSC
