Lattice Semiconductor LatticeMico GPIO Скачать руководство пользователя страница 27

Страница: 27 / 28

LatticeMico8 Microcontroller Software Support

LatticeMico GPIO

Figure 20: Locating a GPIO and Accessing Its Data Register

include "DDStructs.h"
#include "MicoGPIO.h"

int main (void)
{

/* Fetch GPIO instance named 'LED' */
MicoGPIOCtx_t *leds = &gpio_LED;
if (leds == 0) {

/* failed to find a component named "LED" */
return (-1);

}

/* Write 0x1 to programmable I/O pins via the data register

MICO_GPIO_WRITE_DATA_BYTE0 (leds->base, 0x1);

/* Read back the value in the data register */
unsigned char iValue;
MICO_GPIO_READ_DATA_BYTE0 (leds->base, iValue);

return 0;

}

Revision History

Component Version

Description

1.0

Initial release.

3.0 (7.0 SP2)

Cleaned up code. No function change.

3.1

Updated the Edge Capture Register clean method.

Made IRQ Mask register readable.

3.2 (8.1 SP1)

WISHBONE data bus size is configurable to 8 or 32 bits.
Register map is updated to accommodate 8/32-bit
WISHBONE data bus.

3.3

Added LatticeMico8 software support.

3.4

Fixed issues with synthesis when component is configured
for both input and output ports and the widths of each are
different.

3.4

Updated document with new corporate logo.

3.5

Improved modules naming system to support component
scanning function.

Содержание LatticeMico GPIO

Страница 1: ...atures The LatticeMico GPIO includes the following features WISHBONE B 3 interface WISHBONE data base size configurable to 8 or 32 bits wide Four transfer port types tristate input output independent...

Страница 2: ...with inputs only outputs only or both inputs and outputs A bidirectional mode with tristate control is also provided for bidirectional I O pins that are available on the device Bidirectional mode I O...

Страница 3: ...ad from the PIO_DATA register is always delayed one CLK_I cycle from the current state of the PIO_IN port The PIO_DATA read cycle does not prevent the input flip flop from changing state Output Data P...

Страница 4: ...o the input pin transitions from 0 to 1 The edge is detected when the input signal transitions between two WISHBONE clock cycles CLK_I Clearing a bit that is setting it to zero in the edge capture reg...

Страница 5: ...il the interrupt condition is cleared Edge sensitive An IRQ is generated whenever a specific bit in the edge capture register is high and interrupt requests are enabled for that bit in the IRQ_MASK re...

Страница 6: ...eters Table 1 shows the UI parameters available for configuring the LatticeMico GPIO through the Mico System Builder MSB interface HDL Parameters Table 2 describes the parameters that appear in the HD...

Страница 7: ...0X80000000 Port Types Output Ports Only Specifies the transfer mode of PIO ports as output only selected not selected selected Input Ports Only Specifies the transfer mode of PIO ports as input only...

Страница 8: ...selected generates an IRQ on either low to high or high to low transitions selected not selected not selected Positive Edge When selected generates an IRQ on low to high transitions selected not sele...

Страница 9: ...ed for that bit in the IRQ MASK register 0 1 EITHER_EDGE_IRQ With a value of 1 an IRQ is generated on either low to high or high to low transitions 0 1 POSE_EDGE_IRQ With a value of 1 an IRQ is genera...

Страница 10: ...th input and output mode The GPIO s number of output bits is configurable PIO_IO I O 0 X Appears in tristate mode only Each GPIO bit shares one device pin for driving and capturing data The direction...

Страница 11: ...ss Mode Description PIO_TRI DATA_WIDTH 1 0 Read Write This is the PIO read write tristate enable mask Setting a bit to 1 puts the corresponding PIO_IO pin in output mode Setting a bit to 0 puts the co...

Страница 12: ...TURE DATA_WIDTH 1 0 Read Write A bit that is set to 1 indicates that an edge capture event has occurred for that input port The bit is cleared by writing a 0 to the corresponding bit in the EDGE_CAPTU...

Страница 13: ...es interrupt requests when a signal is high or low Figure 8 shows how the GPIO generates interrupt requests when the PIO_DATA signal transitions from low to high After an edge is detected the Edge_Cap...

Страница 14: ...Figure 9 shows how the GPIO generates interrupt requests when the PIO_DATA signal transitions from high to low EBR Resource Utilization The LatticeMico GPIO uses no EBRs Figure 8 IRQ Generation Risin...

Страница 15: ...rrupt requests when the following are detected on an input port High level Positive edge Negative edge The usage scenario depends on the end user application and does not fit within a well known usage...

Страница 16: ...sing word reads unsigned int or signed int As mentioned LatticeMico32 is a big endian microprocessor Therefore from the programmer s perspective the least significant byte of the GPIO will appear in t...

Страница 17: ...rvice Refer to the LatticeMico32 Software Developer User Guide for more information on the device lookup service GPIO Device Context Structure This structure shown in Figure 13 contains GPIO component...

Страница 18: ...s are used If interrupts are not used this value is greater than 31 If interrupts are used the value is 0 31 output_only unsigned int This value is 1 if the GPIO is configured as output only Otherwise...

Страница 19: ...e Context Structure Parameters Continued Parameter Data Type Description Note You may need to access the GPIO device registers directly but some of these registers are write only Implementing shadow r...

Страница 20: ...cture Y is an unsigned int variable reads data register define MICO_GPIO_READ_DATA X Y Y volatile MicoGPIO_t X base data writes data register define MICO_GPIO_WRITE_DATA X Y volatile MicoGPIO_t X base...

Страница 21: ...gisters using the GPIO register structure Using Provided Macros The code example shown in Figure 17 shows how to locate a GPIO device that is instantiated in the platform and how to directly access th...

Страница 22: ...s filled in by the managed build process which extracts GPIO component specific information from the platform definition file The members should not be manipulated directly because the structure is us...

Страница 23: ...value is 0 7 output_only unsigned char This value is 1 if the GPIO is configured as output only Otherwise it is 0 input_only unsigned char This value is 1 if the GPIO is configured as input only Othe...

Страница 24: ...TE2 X Y Y __builtin_import size_t X GPIO_DATA_OFFSET 2 define MICO_GPIO_READ_DATA_BYTE3 X Y Y __builtin_import size_t X GPIO_DATA_OFFSET 3 Macros for writing each byte of the Data Register define MICO...

Страница 25: ...e MICO_GPIO_WRITE_TRISTATE_BYTE2 X Y __builtin_export char Y size_t X GPIO_TRISTATE_OFFSET 2 define MICO_GPIO_WRITE_TRISTATE_BYTE3 X Y __builtin_export char Y size_t X GPIO_TRISTATE_OFFSET 3 Macros fo...

Страница 26: ...CAPTURE_BYTE0 X Y Y __builtin_import size_t X GPIO_EDGE_CAPTURE_OFFSET 0 define MICO_GPIO_READ_EDGE_CAPTURE_BYTE1 X Y Y __builtin_import size_t X GPIO_EDGE_CAPTURE_OFFSET 1 define MICO_GPIO_READ_EDGE_...

Страница 27: ...READ_DATA_BYTE0 leds base iValue return 0 Revision History Component Version Description 1 0 Initial release 3 0 7 0 SP2 Cleaned up code No function change 3 1 Updated the Edge Capture Register clean...

Страница 28: ...ticeECP LatticeECP DSP LatticeECP2 LatticeECP2M LatticeECP3 LatticeECP4 LatticeMico LatticeMico8 LatticeMico32 LatticeSC LatticeSCM LatticeXP LatticeXP2 MACH MachXO MachXO2 MACO mobileFPGA ORCA PAC PA...

Результаты поиска

Содержание LatticeMico GPIO

Отзывы:

Похожие инструкции для LatticeMico GPIO

Бренды по названию

Популярные бренды

Lattice Semiconductor LatticeMico GPIO, Руководство пользователя

Результаты поиска

Содержание LatticeMico GPIO

Отзывы:

Похожие инструкции для LatticeMico GPIO

Бренды по названию

Популярные бренды