Register Definitions
10
LatticeMico GPIO
Register Definitions
The LatticeMico GPIO includes the registers shown in Table 4. See
for examples that show how to access these
registers in order to access the programmable I/O pins.
GPIO_STB_I
High
I
X
Strobe input. When asserted, indicates that the
SLAVE is selected.
GPIO_WE_I
—
I
X
Write signal. Value of 1 is used for a write and 0
for a read.
GPIO_ACK_O
High
O
0
Acknowledge output. When asserted, indicates
normal cycle termination.
GPIO_DAT_O
—
O
0
Data output array
PIO Interface Ports
PIO_IN
—
I
X
Appears in input mode or both input and output
mode. The GPIO’s number of input bits is
configurable.
PIO_OUT
—
O
0
Appears in output mode or both input and output
mode. The GPIO’s number of output bits is
configurable.
PIO_IO
—
I/O
0/X
Appears in tristate mode only. Each GPIO bit
shares one device pin for driving and capturing
data. The direction of each pin is individually
selectable. The PIO_IO is an input when the
corresponding PIO_TRI register bit is cleared (0).
Other Auto-connected Internal Signals
IRQ_O
High
O
0
Interrupt request outputs. The GPIO can be
configured to generate an IRQ on certain input
conditions.
Table 3: GPIO I/O Ports (Continued)
Port Name
Active
Direction
Initial State
Description
Table 4: Register Map
Register Name
Offset
Address Offset within Register Word
Description
0x0
0x1
0x2
0x3
PIO_DATA
0x00
PIO_IN/OUT/
IO[7:0]
PIO_IN/OUT/
IO[15:8]
PIO_IN/OUT/
IO[23:16]
PIO_IN/OUT/
IO[31:24]
I/O Data
PIO_TRI
0x04
[7:0]
[15:8]
[23:16]
[31:24]
Tristate control
IRQ_MASK
0x08
[7:0]
[15:8]
[23:16]
[31:24]
IRQ Mask
EDGE_CAPTURE
0x0C
[7:0]
[15:8]
[23:16]
[31:24]
Edge Capture
