Timing Diagrams
12
LatticeMico GPIO
Timing Diagrams
The timing diagrams featured in Figure 5 through Figure 9 show the timing of
the GPIO’s WISHBONE and external signals.
Figure 5 shows how the GPIO’s master ports update the data in the internal
register.
Table 8: EDGE_CAPTURE Register Bit Definition
Register Name
Bit
Access Mode Description
EDGE_CAPTURE
DATA_WIDTH -1:0 Read/Write
A bit that is set to 1 indicates that an edge capture event
has occurred for that input port.
The bit is cleared by writing a 0 to the corresponding bit
in the EDGE_CAPTURE register or by disabling and then
enabling the corresponding bit in the IRQ_MASK register.
After an edge is detected, the EDGE_CAPTURE bit is
held at 1 until explicitly cleared.
Example: If a byte read from address offset 0 returns
0x01, then an edge capture event occurred for PIO_IN/
IO[0]
Figure 5: WISHBONE Master Writes Data in the Internal Register
