4
ispMACH 4000ZE Pico Development Kit
Lattice Semiconductor
User’s Guide
Software Requirements
Install the following software before you begin developing designs for the evaluation board:
• ispLEVER
®
Classic 1.3 (ispMACH 4000ZE CPLD support)
• PAC-Designer
®
5.1 (ispPAC-POWR6AT6 mixed-signal PLD support)
• ispVM™ System 17.5 (Required for re-programming on-board PLDs)
• PicoView 1.04 (Required for the I
2
C GPIO Expansion Demo)
ispMACH 4000ZE Device
This board features the ispMACH 4000ZE CPLD which is ideal for ultra low-power, high-volume portable applica-
tions. The on-board LC4256ZE is the highest capacity of the family with 256 macrocells. The 144-pin csBGA pack-
age provides 108 user I/Os and four dedicated inputs in a 7mm x 7mm package. The LC4256ZE consumes
standby current as low as 15µA. A complete description of this device can be found in the
ispMACH 4000ZE Family
Data Sheet
.
Demonstration Designs
Lattice provides two demos that illustrate key applications of the ispMACH 4000ZE CPLD device in the context of a
consumer electronics application:
•
Pico Power
– Integrates an up/down counter, a right/left shift register, voltage/current meter display, and an I
2
C
bus master controller that communicates with the on-board POWR6AT6 Power Manager II device. The
POWR6AT6 provides analog power supply monitoring and a 2-wire I
2
C interface to measure various voltage sup-
plies of the board. An LCD panel displays demo output using three characters. You can select demo features
with the keyboard-style 4-bit DIP switch bank. The Pico Power demo is designed for battery operation but if one
isn’t available you can power the board by connecting the USB cable provided to a PC USB port.
•
GPIO I
2
C Expansion
– Shows an application of the LC4256ZE device as an I
2
C slave processing instructions
issued by a CPU/MPU. CPLDs are ideal GPIO “expanders” for processors. Control registers of the CPLD’s I
2
C
module allow the processor to access counter and shift registers, I/O, and power measurements. An I
2
C software
interface utility, PicoView, emulates the CPU/MPU component of the system. Visit
www.latticesemi.com/4000ze-
pico-kit
to download PicoView.
Note: It is possible that you will obtain your Pico board after it has been reprogrammed. To restore the factory
default demo and program it with other Lattice-supplied examples, see the Download Demo Designs section of this
document.
Pico Power Demo
The Pico Power design highlights low-power features of the LC4256ZE CPLD along with inexpensive PCB design
techniques that help extend battery life, such as low-speed CPLD clocking, efficient use of the CPLD I/O cell’s I/O
bus maintenance feature, and gated supply rails. The demo design integrates an I
2
C master reference design
(
www.latticesemi.com/products/intellectualproperty
) with LCD controller logic, an up/down counter and left/right
shift register modules. You may switch the LCD display between a current/voltage meter and counter/shifter opera-
tion using the DIP switch bank. The demo shows a clock generator based on the LC4256ZE on-chip oscillator and
timer (OSCTIMER) hardware feature. The counter and shift register modules can be clocked at either <2 Hz or 5
MHz to help illustrate the difference in dynamic power demands.
Current and voltage monitoring of the Pico board is provided by the POWR6AT6 mixed-signal PLD and on-board
sensor circuits (see AN6049,
High-side Current Sensing Techniques for Power Manager Devices
). To minimize
power consumption of the overall system, the POWR6AT6 supply rail is powered on momentarily by the LC4256ZE
whenever a current or voltage display is requested or after the Pico board is reset.
