Switch 1234 (Demo)
Pico Power Demo Features
0000 (Up)
0001 (Down)
Decimal Up/Down Counter Display
– Displays an 8-bit decimal up/down counter (0.0-9.9) using
the <2 Hz clock generated by the LC4256ZE On-Chip Oscillator and Timer (OSCTIMER). A 4-bit
nibble is committed to the “ones” and “tenths” position of the LCD. The down counter will be initial-
ized to 9.9 and up counter to 0.0 upon power-up, reset or if the count rolls over.
Slow clock <2 Hz:
1100 (VMON1 Icccore)
1001 (VMON2 Iccio)
Fast Clock 5 MHz:
1000 (VMON1 Icccore)
Current Meter Display
– Displays current measurements of the LC4256ZE 1.8V core and 2.5V
I/O supply rails. To help illustrate the relative dynamic power requirements of the board at <2 Hz or
5 MHz, Icccore can be measured at both clock frequencies.
The current meter circuit includes a high-side current sensor amp and the POWR6AT6 mixed-sig-
nal PLD which provides the voltage monitor, analog-to-digital conversion (ADC), and an I
2
C slave
to register the measurement. The entire circuit is dynamically energized whenever the current
meter function is selected or the Pico board push-button is pressed. Note that the additional draw
of the meter circuit is factored into the display latched into the LCD panel by the CPLD. This will
result in an additional 100-600 microamp over static measurements taken on the board at the
Icccore and Iccio shunts R35 and R34.
0010 (Shift Left)
0011 (Shift Right)
Left/Right Shift Register Display
– Displays a shift register operating as serial-in, parallel-out
using the <2 Hz clock source. Each bit of the register is associated with the corresponding seg-
ment of the 7-segment LCD such that reg(21) = Segment 7 of the left-most character and reg(0) =
Segment 1 of the right-most character.
When shifting left, the register will shift in ‘0’ to the MSB upon each clock. When shifting right the
register shifts in ‘0’ to the LSB. The shift register will be initialized to 1FFFFEh upon power-up,
reset, or if the shift result rolls over.
1010 (VMON5 5V USB)
1011 (VMON6 3V Battery)
Volt Meter
– Displays voltage measurements of the 5V USB interface or the 3V button-cell battery.
The volt meter function dynamically activates the POWR6AT6 supply rail in the same manner as
the Current Meter Display function.
1111 (Standby)
Standby Mode
(Default)
– Demonstrates standby power of the LC4256ZE. No LCD output is
available in this mode.
In battery-powered, standby mode CPLD core current draw is ~10µA.
Other
Reserved
switch settings. No LCD output.
Push Button Switch
Pico Power Demo Feature
SW1
Manual Reset
is a push-button switch (SW1) used to assert a manual reset of the demo. All
design modules including the CPLD OSCTIMER will be initialized when SW1 is pressed.
6
ispMACH 4000ZE Pico Development Kit
Lattice Semiconductor
User’s Guide
Run the Pico Power Demo
Follow the procedure below to explore the Pico Power demonstration on the evaluation board.
1.
Select Switch Bank pattern 1111 (Standby)
The Pico board activates the LC4256ZE standby mode. To measure the current draw of the CPLD core
(Icccore), touch voltmeter leads across R35, read the voltage drop, and then divide by 50 Ohms (I=V/R). The
LC4256ZE draws approximately 10µA in Standby mode. Given a new button-cell battery the Pico board should
be operational for approximately one year in standby mode. As a further measure to minimize CPLD current
draw, I/O Bus Maintenance features are disabled and the DIP switch input is designed to pull input high rather
than open, high-Z. This will avoid current leakage by the CPLD buffers by disabling the internal pull-down resis-
tor circuits.
2.
Select Switch Bank pattern 1100 (Low-speed CPLD core current meter)
The LCD displays CPLD core current (Icccore) in microamp (µA) units. The CPLD control logic performs the
following operations to arrive at the result. First, the counter and the shift register modules of the CPLD are
enabled by the internal slow clock (<2Hz) and the ispPAC-POWR6AT6 power supply rail is enabled. Next, the
I
2
C master module issues three I
2
C bus cycles to initiate and read the analog-to-digital conversion result of the
POWR6AT6 voltage monitor input (VMON1). Finally, the data is displayed on the LCD in microamp units. The
POWR6AT6 VMON1 is driven by a high-side current sense circuit connected to the CPLD Vcccore supply rail.
Power consumption of the CPLD in the slow speed operation is in the µA range. Note that a volt meter reading
across R35 will reflect current draw after the POWR6AT6 has powered off and therefore be 100-600 micro-
amps less than the value latched by the CPLD.
