Lattice Semiconductor ispLever Core Multi-Channel DMA Controller, Руководство пользователя, Страница: 8 / 29

Lattice Semiconductor Multi-Channel DMA Controller User’s Guide
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Memory-to-Memory Read
Transfer State Three - S13
This is the third state of the memory-to-memory transfer. The state machine sam-
ples the ready signal and stays in this state as long as it is asserted. The machine
transitions to state S14 when the ready signal is de-asserted.
Input Signals:
eopin_n
,
ready
Asserted Output Signals:
memr_n
,
address
Possible State Transitions: S13, S14
Memory-to-Memory Read
Transfer State Four - S14
This is the fourth stage of the memory-to-memory transfer. The state machine de-
asserts
memr_n
signal and asserts an enable signal to flop the incoming data into
the temporary register. The state machine transitions to state S21, which is the first
state of the memory-to-memory write transfer stage.
Input Signals:
eopin_n
Asserted Output Signals: none
Possible State Transitions: S21
Memory-to-Memory Write
Transfer State One - S21
This is the fifth stage of the memory-to-memory transfer mode. In the 8237 mode,
the content of the current address register on Channel 1 is put on the address bus.
In the non-8237 mode, the content of the destination address register on the chan-
nel being serviced is put on the address bus. The
memr_n
and
memw_n
signals are
de-asserted. The state machine transitions to state S22.
Input Signals:
eopin_n
Asserted Output Signals:
address
Possible State Transitions: S22
Memory-to-Memory Write
Transfer State Two - S22
This is the fifth state of memory-to-memory transfer. The state transitions to state
S23.
Input Signals:
eopin_n
Asserted Output Signals:
address
Possible State Transitions: S23
Memory-to-Memory Write
Transfer State Three - S23
This is the seventh state of the memory-to-memory transfer. The
memw_n
signal is
asserted, and the content of the temporary register is placed on the data bus. The
state machine samples the ready signal and stays in this state as long as it is
asserted. Then the machine transitions to state S24.
Input Signals:
eopin_n
,
ready
Output Signals:
memw_n
Possible State Transitions: S23, S24
Table 2. State Descriptions (Continued)
State Description