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Lattice Semiconductor

Multi-Channel DMA Controller User’s Guide

26

Appendix for LatticeECP™ and LatticeEC™ FPGAs

Table 22. Performance and Resource Utilization

1

Supplied Netlist Configurations

The Ordering Part Number (OPN) for all configurations of this core in LatticeEC devices is DMA-MC-E2-N3.
Table 23 lists the Lattice-specific netlists that are available in the Evaluation Package, which can be downloaded
from the Lattice web site at www.latticesemi.com.

Table 23. Core Configuration

You can use the IPexpress software tool to help generate new configurations of this IP core. IPexpress is the Lattice
IP configuration utility, and is included as a standard feature of the ispLEVER design tools. Details regarding the
usage of IPexpress can be found in the IPexpress and ispLEVER help system. For more information on the
ispLEVER design tools, visit the Lattice web site at: www.latticesemi.com/software.

Mode

Name of

Parameter File

SLICEs

LUTs

sysMEM 

EBRs

Registers

I/O

f

MAX

 (MHz)

8237

dma_mc_e2_3_001.lpc

710

1087

0

551

59

72

Non-8237

dma_mc_e2_3_002.lpc

1633

2249

0

1181

125

86

1. Performance and utilization characteristics are generated using LFEC20E-4F672C in Lattice ispLEVER 4.1 software. When using this IP 

core in a different density, package, or speed grade, performance may vary.

Name of

Parameter File

Number of Channels

Data Bus Width

Address Bus Width

Word Count Width

8237 Mode

dma_mc_e2_3_001.lpc

4

8

16

16

Non-8237 Mode

dma_mc_e2_3_002.lpc

4

32

32

16

Содержание ispLever Core Multi-Channel DMA Controller

Страница 1: ...February 2006 ipug11_04 0 Multi Channel DMA Controller User s Guide ispLever CORE CORE TM...

Страница 2: ...om the Intel 8237A core in the following ways The bi directional ports are split into separate input and output ports MCDMA does not support the cascade mode of operation The latch that holds the uppe...

Страница 3: ...Lattice Semiconductor Multi Channel DMA Controller User s Guide 3 Software DMA requests...

Страница 4: ...the data bus CPU Interface Data The CPU Interface Data block contains all the configuration registers It includes all the routing logic required to transfer either the selected register s contents du...

Страница 5: ...3 S14 S21 S22 S23 and S24 If the next transfer should continue for the same request the path from S11 to S24 is repeated If memory to I O or I O to memory is enabled the FSM goes through states S2 S3...

Страница 6: ...Modes Request Dropped Illegal Mode Illegal I O Mode 8237 only LAST_TRAN SINGLE_TRAN Termination LAST_TRAN SINGLE_TRAN Termination Write Phase Read Phase Another Transfer Compressed 8237 only NR NR NR...

Страница 7: ...ty at that time The DMA priority scheme will be described more in the priority request encoder section Non 8237 Mode In this mode memory to memory transfer is detected if bit zero of the current chann...

Страница 8: ...f the memory to memory transfer mode In the 8237 mode the content of the current address register on Channel 1 is put on the address bus In the non 8237 mode the content of the destination address reg...

Страница 9: ...the DMA transfer The dack signal is asserted The dreq signal does not need to be held asserted after this state if block or single transfer mode is selected memr_n or iorout_n is asserted depending on...

Страница 10: ...ns are addressable but I O locations are not addressable The source address register in the non 8237 mode holds the memory location address during DMA transfers between an I O device and memory Active...

Страница 11: ...est register The internal registers of the core are accessible during the idle state SI when no channel is requesting service and no DMA transfers are in progress The core operates in two cycles Idle...

Страница 12: ...e MODE_8237 Defines the DMA mode If it is TRUE the DMA will be in 8237 mode otherwise it will be in non 8237 mode TRUE FALSE Number of Channel NUM_CHANNELS Sets the number of channels In 8237 mode it...

Страница 13: ...ters In the 8237 mode ain is 4 bits wide In the non 8237 mode the bus width depends on the number of channels selected dbin DATA_BUS_WIDTH 1 0 Input N A Data Bus Input The CPU writes to the internal r...

Страница 14: ...n and iorin_n are asserted Clock edges 1 2 and 3 indicate the edges on which the data is valid aen Output High Address Enable This active high signal enables the 8 bit latch that contains the upper 8...

Страница 15: ...Lattice Semiconductor Multi Channel DMA Controller User s Guide 15 Figure 4 Processor Read Timing Waveform Clock cs_n iorin_n ain 1 2 3 dbout...

Страница 16: ...ss Si Note 1 This timing diagram demonstrates the extended write operation In the 8237 mode when normal write operation is selected iowout_n or the memw_n is asserted one clock cycle later If compress...

Страница 17: ...ialization is enabled the value in the Base Word Count register is reloaded at the end of the DMA service When the value in the register goes from zero to 0xFFFF a terminal count eopout_n signal is ge...

Страница 18: ...r master clear clears this register The channel must be in block mode in order to make a software request Table 10 lists the request register format in 8237 Mode Status Register This register is only...

Страница 19: ...ress increment 1 Address decrement 7 6 10 Demand mode select 01 Single mode select 10 Block mode select 11 Cascade mode unsupported Bit Description 0 0 Channel 0 unmasked 1 Channel 0 masked 1 0 Channe...

Страница 20: ...in consecutive cycles after clearing the byte pointer The number of cycles taken to access this register depends on the size of the address bus During memory to memory transfers this register stores...

Страница 21: ...s the channel s hardware requests Auto initialization is disabled upon a reset Table 13 Command Register Non 8237 Mode Table 14 Mode Register Non 8237 Mode Bit Description 0 0 Controller enable 1 Cont...

Страница 22: ...0 0 0 1 Base and current Word Count reg Current Word Count reg 0 0 1 0 1 Base and current Address reg Current DMA address reg 0 0 1 1 Base and current Word Count reg Current Word Count reg 0 1 0 0 2...

Страница 23: ...of the bits select which channel to be programmed Program the Mode and Channel control registers of all the channels Write into the Address registers and Word Count register Enable the controller The...

Страница 24: ...PFUs2 Registers sysMEM EBRs I O fMAX MHz 8237 dma_mc_o4_2_001 lpc 1258 200 524 N A 59 58 Non 8237 dma_mc_o4_2_002 lpc 2661 499 1187 N A 125 66 1 Performance and utilization characteristics are genera...

Страница 25: ...ng the usage of IPexpress can be found in the IPexpress and ispLEVER help system For more information on the ispLEVER design tools visit the Lattice web site at www latticesemi com software Mode Name...

Страница 26: ...nd is included as a standard feature of the ispLEVER design tools Details regarding the usage of IPexpress can be found in the IPexpress and ispLEVER help system For more information on the ispLEVER d...

Страница 27: ...cluded as a standard feature of the ispLEVER design tools Details regarding the usage of IPexpress can be found in the IPexpress and ispLEVER help system For more information on the ispLEVER design to...

Страница 28: ...d is included as a standard feature of the ispLEVER design tools Details regarding the usage of IPexpress can be found in the IPexpress and ispLEVER help system For more information on the ispLEVER de...

Страница 29: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Lattice DMA MC E2 N3 DMA MC O4 N2 DMA MC XM N3 DMA MC XP N2 DMA MC SC N3...

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