Lattice Semiconductor iCE40LM4K, Руководство пользователя

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5 5
4 4
3 3
2 2
1 1
D
D
C
C
B
B
A
A
SPI CONFIGURATION / FLASH
LATTICE SEMICONDUCTOR CORPORATION CONFIDENTIAL
AP (DRAGON BOARD) INTERCONNECT
Note position of pin#1 in reference board
Note position of pin#1 in reference board
Note: Place close to DUT
Note: Place close to DUT
Note: Place close to DUT
DUT
Default: Shunt
For programming Flash - Shunt 1,3 and 2,4 (default) For programming iCE - Shunt 3,4 and 1,2
Default: Shunt
Default: Shunt
Default: Open
Default: Shunt
Default: Shunt 1,2 (for IR LED)
SENSOR FUSION DEMO BOARD (iCE40LP3K5-WLCSP25)
pr
oc_sdi
pr
oc_sdo
pr
oc_i
n
tr
pr
oc_scl
k
pr
oc_cs
CRST
b
CDO
N
E
CRST
b
CDO
N
E
pool
A_sen
sor
_SCL
pool
A_sen
s
or
_SDA
fl
sh
_cs
fl
sh_m
osi
fl
s
h
_
s
cl
k
fl
s
h
_
m
is
o
fl
s
h
_
m
o
s
i
fl
s
h
_
m
is
o
fl
s
h
_
s
cl
k
pool
B_sen
s
or
_SCL
pool
B_sen
s
or
_SDA
fl
sh
_cs
fl
sh_sc
lk
pr
oc_sdo
pr
oc_sdi
pr
oc_i
n
tr
pr
oc_scl
k
pr
oc_cs
BAR_LED BAR_LED_M
U
X
_IR_LED
IR_LED
BAR_LED_M
U
X
_IR_LED
CRST
b
fl
sh
_cs
fl
sh_m
osi
ic
e
_
S
O
ic
e
_
S
I
ice_SO fl
s
h
_
m
is
o
ice_SI
IR_I
N
GPIO_C5
GPIO_C5
sen
s
or
0_XCLR
Hall_
o
u
t
CRST
b
DRG
N
5
V
V
CC3
V
3
V
CCIO0
V
CCIO2
V
CCIO0
V
CC1
V
2
V
CC3
V
3
pool
B_sen
s
or
_SDA
Pg[
3
]
pool
B_sen
sor
_
SCL
Pg[
3]
pool
A_sen
sor
_SDA
Pg[
2
]
pool
A_sen
sor
_SCL
Pg[
2
]
fl
sh
_cs
Pg[
5
]
IR_I
N
Pg[
3
]
IR_LED
Pg[
3
]
CRST
b
Pg[
5
]
cl
k
Pg[
3
]
fl
sh
_cs
Pg[
5
]
BAR_LED
Pg[
3]
CDO
N
E
Pg[
5
]
Hall_
o
u
t
Pg[
2]
fl
sh
_mi
s
o
Pg[
5
]
fl
sh
_scl
k
Pg[
5
]
fl
sh
_cs
Pg[
5
]
fl
sh
_mosi
Pg[
5
]
sen
s
or
0_XCLR
Pg[
2
]
Ti
tl
e
Si
z
e
Doc
u
men
t
Nu
m
b
er
Re
v
Da
te
:
S
h
eet
of
102-
374A-
0913
2
FPGA,
Con
fi
g
Fl
a
s
h
, AP In
te
rc
on
n
e
ct
s
B
45
Sa
t
u
rd
ay, O
c
to
b
er
05,
2013
Ti
tl
e
Si
z
e
Doc
u
men
t
Nu
m
b
er
Re
v
Da
te
:
S
h
eet
of
102-
374A-
0913
2
FPGA,
Con
fi
g
Fl
a
s
h
, AP In
te
rc
on
n
e
ct
s
B
45
Sa
t
u
rd
ay, O
c
to
b
er
05,
2013
Ti
tl
e
Si
z
e
Doc
u
men
t
Nu
m
b
er
Re
v
Da
te
:
S
h
eet
of
102-
374A-
0913
2
FPGA,
Con
fi
g
Fl
a
s
h
, AP In
te
rc
on
n
e
ct
s
B
45
Sa
t
u
rd
ay, O
c
to
b
er
05,
2013
J4
BAR_IR_SEL
J4
BAR_IR_SEL
1 2 3
C15
1
u C15
1
u
R40 10k R40 10k
R2
0
R2
0
J11 FLSH
E
N
J11 FLSH
E
N
1 2
S
W
1
CRST
S
W
1
CRST
C19
0.
1
u
C19
0.
1
u
J
8
IDD_BOT J
8
IDD_BOT
1
2
C17
10n
C17
10n
R12 10k R12 10k
D3 DO
N
E
D3 DO
N
E
J21 AP I
N
TERCO
NN
ECT
J21 AP I
N
TERCO
NN
ECT
2 4 6 8
10
1 3 5 7 9
C16
10n
C16
10n
C22
1
u
C22
1
u
R30 2k
2
R30 2k
2
R41
0
R41
0
R10 10k R10 10k
C1
8
0.
1
u
C1
8
0.
1
u
J13 SPI PGM J13 SPI PGM
SS2
1
G
N
D1
2
SS3
3
N
C2
4
MI
S
O
5
N
C1
6
SC
L
K
7
MO
S
I
8
SS1
9
G
N
D2
10
C21
1
u
C21
1
u
TOP BANK
BOT BANK
CONFIG SPI
iCE40LP3k5-WLCSP25
iCE40LP3k
5
-
W
LCSP25
U1
1
TOP BANK
BOT BANK
CONFIG SPI
iCE40LP3k5-WLCSP25
iCE40LP3k
5
-
W
LCSP25
U1
1
IO
B2
E5
IO
B3
D5
IO
B4
E4
IO
B5
C5
IO
B
11_G
5
E3
IO
B
12_G
4
C4
IO
B1
6
D3
CDO
N
E
C3
CRS
T
B
B3
IO
B
22_S
O
D2
IO
B
23_S
I
C1
IO
B
24_S
C
LK
D1
IO
B
25_S
S
E1
IO
T
2
8
A1
IO
T
3
0
B1
IO
T
3
1
C2
IO
T
45_G
1
A3
IO
T
46_G
0
A4
IO
T
5
5
B5
IO
T
5
6
A5
A
V
DD/
V
CC
B4
V
CCIO
0
A2
G
N
D1
D4
V
CCIO
2
/S
P
I
V
CC
E2
G
N
D2
B2
M2
5
P
8
0
U
8
M2
5
P
8
0
U
8
SD
I
5
SC
K
6
W
P
3
CS
1
SD
O
2
HO
L
D
7
8
V
CC
4
G
N
D
J19 IDD_TOP J19 IDD_TOP
1
2
J1
8
IDD_CORE J1
8
IDD_CORE
1
2
C3
8
0.
1
u
C3
8
0.
1
u
C14
0.
1
u
C14
0.
1
u
J16
MA
/ S
L
J16
MA
/ S
L
3 4
1 2
R
8
10k R
8
10k
J5
IR M
U
X
J5
IR M
U
X
1 2 3
R22 2k
2
R22 2k
2
C11
10n
C11
10n
J10
CRST
J10
CRST
1
2