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Programming Cables 

 

 

User Guide 

 

© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at 

www.latticesemi.com/legal

 

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

 

FPGA-UG-02042-26.2 

3.

 

Programming Cable Pin Definitions 

The functions provided by the programming cables correspond with available functions on Lattice programmable 
devices. Since some devices contain different programming features, the specific functions provided by the 
programming cable may depend on the selected target device. ispVM System/Diamond Programmer software 
automatically generates the appropriate functions based on the selected device. See 

Table 3.1

 for an overview of the 

programming cable functions. 

Table 3.1. Programming Cable Pin Definitions 

Programming Cable Pin 

Name 

Programming Cable Pin Type 

Description 

VCC 

Programming 
Voltage 

Input 

Connect to V

CC

 or V

CCJ

 plane of the target device. 

Typical ICC = 10 mA. Your board design supplies 
the power for V

CC

. Note: This may not be the 

same as a target device’s V

CCO

 plane. 

TDO/SO 

Test Data 
Output 

Input 

Used to shift data out via the IEEE1149.1 (JTAG) 
programming standard. 

TDI/SI 

Test Data Input 

Output 

Used to shift data in via the IEEE1149.1 
programming standard. 

ispEN/PROG/SN 

Enable 

Output 

Enable device to be programmed. 
SN = SSPI Chip select for HW-USBN-2B 

TRST 

Test Reset 

Output 

Optional IEEE 1149.1 state machine reset. 

DONE 

DONE 

Input 

DONE indicates status of configuration 

TMS 

Test Mode 
Select Input 

Output 

Used to control the IEEE1149.1 state machine. 

GND 

Ground 

Input 

Connect to ground plane of the target device 

TCK/SCLK 

Test Clock Input 

Output 

Used to clock the IEEE1149.1 state machine 

INIT 

Initialize 

Input 

Indicates device is ready for configuration to 
begin. INITN is only found on some devices. 

I2C: SCL* 

I

2

C SCL 

Output 

Provides the I

2

C signal SCL 

I2C: SDA* 

I

2

C SDA 

Output 

Provides the I

2

C signal SDA. 

5 V Out* 

5 V Out 

Output 

Provides a 5 V signal for the iCEprogM1050 
Programmer. 

*Note: Only found on the HW-USBN-2B cable. 

TRST

GND

*

TMS

*

TDI/SI

*

TDO/SO

*

ISPEN/PROG/SN

VCC

*

5 V OUT

I

2

C: SCL

TCK/SCLK

*

I

2

C: SDA

DONE

* Indicates flywire connections required for most basic JTAG programming.

 

Figure 3.1. Programming Cable In-System Programming Interface for the PC (HW-USBN-2B)* 

*Note

Requires Diamond Programmer 3.1 or later

Содержание HW-USBN-2B

Страница 1: ...Programming Cables User Guide FPGA UG 02042 26 2 May 2019...

Страница 2: ...faults and all risk associated with such information is entirely with Buyer Buyer shall not rely on any data and performance specifications or parameters provided herein Products sold by Lattice have...

Страница 3: ...information herein are subject to change without notice FPGA UG 02042 26 2 3 Contents 1 Features 5 2 Programming Cables 5 3 Programming Cable Pin Definitions 6 4 Programming Software 8 5 Target Board...

Страница 4: ...2A 7 Figure 3 3 Programming Cable In System Programming Interface for the PC HW DLN 3C and Equivalents 7 Figure 3 4 Programming Cable In System Programming Interface for the PC pDS4102 DL2 or pDS4102...

Страница 5: ...ion Figure 1 1 USB Cable HW USBN 2B 2 Programming Cables Lattice Programming Cable products are the hardware connection for in system programming of all Lattice devices After you complete your logic d...

Страница 6: ...power for VCC Note This may not be the same as a target device s VCCO plane TDO SO Test Data Output Input Used to shift data out via the IEEE1149 1 JTAG programming standard TDI SI Test Data Input Ou...

Страница 7: ...Yellow Green Purple Black White 61 25 pin Parallel Port Adapter HW7265 DL3 and HW7265 DL3A Grey Housing with RJ 45 Connector OtherCables are Labeled withPart Number To PC Figure 3 3 Programming Cable...

Страница 8: ...ice families that feature low power it is recommended to add a 500 resistor between VCCJ and GND during the programming interval when a USB programming cable is connected to a very low power board des...

Страница 9: ...N PROG na TRST OUTPUT VCC GND na Orange Brown Purple White Yellow Green Red Black Programming cable pin type Target Board Recommendation Output Input Output Output Output Input Input Output Input Inpu...

Страница 10: ...Output Input Input Output Input Input Output Output Output 4 7 k Pull Up 4 7k Pull Down Note 1 Note 2 Note 3 Note 3 Connect the programming cable wires above to the corresponding device or header pins...

Страница 11: ...al ICC 10 mA For devices that have a VCCJ pin the VCCJ must be connected to the cable s VCC For other devices connect the appropriate bank VCCIO to the cable s VCC A 0 1 F decoupling capacitor is requ...

Страница 12: ...x Select the Set High radio button If the proper option is not selected the TRST pin is driven low by ispVM Diamond Programmer Consequently the BSCAN chain does not work because the chain is locked in...

Страница 13: ...X X X X X 2 5 3 3 V Support X X X X X X X X X X 5 0 V Support X X X X X X X X X 2 x 5 Connector X X X X X X X 1 x 8 Connector X X X X X X X Flywire X X X X X X Lead free Construction X X X Available...

Страница 14: ...try to install its own drivers that may not work If you have attempted to connect the PC to the USB cable without first installing the appropriate drivers or have trouble communicating with the Latti...

Страница 15: ...marks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA UG 02042 26 2 15 Figure A 3 Update Driver Software Browse...

Страница 16: ...n herein are subject to change without notice 16 FPGA UG 02042 26 2 For Diamond installations browse to lscc diamond data vmdata drivers Click Next Select Install this Driver software anyway The syste...

Страница 17: ...trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice FPGA UG 02042 26 2 17 Figure A 8 Installation Completed...

Страница 18: ...C SDA value Changed ASC to L ASC10 Updated footnote 4 to include ispClock devices Adjusted trademarks Revision History Updated format Back cover Updated template Minor editorial changes Revision 26 1...

Страница 19: ...ispEN Enable PROG SN and its description revised Updated Figure 2 Programming Cable In System Programming Interface for the PC HW USBN 2B Programming Cable ispEN Pin In Table 4 Programming Cable Feat...

Страница 20: ...nt transferred to user s guide format Features Added Figure USB Cable HW USBN 2A Programming Flywire and Connection Reference Updated Recommended Cable Connections table for MachXO2 devices Target Boa...

Страница 21: ...www latticesemi com...

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