CrossLink Programming and Configuration Usage Guide
Technical Note
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FPGA-TN-02014-1.2
4.7.
Clearing the Configuration Memory and Re-initialization
The current User Mode configuration of CrossLink remains in operation until it is actively cleared, or power is lost.
Several methods are available to clear the internal configuration memory of CrossLink:
Remove power and reapply power.
Execute an Erase command while in programming mode
Toggle the CRESETB pin from HIGH to LOW. Note that only a HIGH to LOW transition creates a Refresh command.
Keeping CRESETB LOW does not create a refresh event.
Reinitialize the memory through a Refresh command. Any active configuration port can be used to send a Refresh
command.
Invoking one of these methods causes CrossLink to drive CDONE LOW. CrossLink enters the initialization state as
described earlier.
4.8.
Bitstream/PROM Sizes
CrossLink is an SRAM based FPGA. The SRAM configuration memory must be loaded from a non-volatile memory that
can store all of the configuration data. The size of the configuration data is variable. It is based on the amount of logic
available in the FPGA, and the number of pre-initialized Embedded Block RAM (EBR) components. A CrossLink design
using the largest device, with every EBR pre-initialized with unique data values, and generated without compression
turned on requires the largest amount of storage.
Table 4.2. Maximum Configuration Bits
Device
Bitstream Size Without Pre-Initialized EBR
Bitstream Size With Maximum Number of
Pre-Initialized EBR
Units
LIF-MD6000
1.24
1.59
Mb
4.9.
Configuration Modes of CrossLink
The CrossLink configuration SRAM memory must be loaded with valid configuration data before the FPGA operates.
CrossLink provides four modes of loading the configuration data into the SRAM memory. The four modes available are
Self-Download (NVCM) mode, Master SPI mode, Slave SPI mode and Slave I
2
C Configuration mode. Dual-boot operation
is supported as a combination of the Self-Download mode and Master SPI mode.
4.10.
sysCONFIG Pins
CrossLink provides a set of sysCONFIG I/O pins to program and configure the FPGA. The sysCONFIG pins are grouped
together to create ports (that is SSPI, I
2
C, MSPI) that are used to interact with the FPGA for programming,
configuration, and access of resources inside the FPGA. The sysCONFIG pins in a configuration port group may be
active, and used for programming the FPGA, or they can be reconfigured to act as general purpose I/O.
Recovering the configuration port pins for use as general purpose I/O requires adhering to the following guidelines:
You must DISABLE the unused port. You can accomplish this by using the Diamond Spreadsheet View’s Global
Preferences tab. Each configuration port is listed in the sysCONFIG options tree.
You must prevent external logic from interfering with device programming by ensuring that recovered sysCONFIG
pins are not asserted when CrossLink is in Feature Row HW Default Mode state.
lists the default state of the shared sysCONFIG pins. A device with an erased/HW default Feature Row has the
SPI Slave and I
2
C ports enabled. Upon entry to User Mode, the state of the SSPI and I
2
C ports is determined by the
sysCONFIG port settings. The SW default sysCONFIG port setting is SSPI is enabled while I
2
C is disabled. This means you
lose the ability to program CrossLink using I
2
C when using the default sysCONFIG port settings. You must assert
CRESETB to program over I
2
C in that case. To retain the I
2
C sysCONFIG pins in User Mode, be sure to ENABLE them
using the Diamond Spreadsheet View editor.
The sysCONFIG pins are powered by the VCCIO0 voltage. It is important that you take this into consideration when
provisioning other logic attached to Bank 0.
