Lattice Semiconductor CrossLink, Руководство по программированию и настройке

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CrossLink Programming and Configuration Usage Guide
Technical Note
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FPGA-TN-02014-1.2 11
Table 4.3. Default State of sysCONFIG Pins
Pin Name
Associated
sysCONFIG Port
Pin Function in
Feature Row Blank Mode
(Configuration Mode)
Pin Direction
(Configuration Mode)
Default Function
in User Mode
(Software Default
State)
CRESETB SDM CRESETB Input with weak pull up CRESETB
CDONE SDM I/O I/O with weak pull up User-defined I/O
SPI_SCK/MCK/SDA SSPI/MSPI/I 2 C SSPI/I 2 C Input with weak pull up SSPI
SPI_SS/CSN/SCL SSPI/MSPI/IC SSPI/I 2 C Input with weak pull up SSPI
MOSI SSPI/MSPI SSPI Input SSPI
MISO SSPI/MSPI SSPI Output SSPI
Note: All pins are in Configuration Mode until the device is configured and enters User Mode.
Table 4.4. Default State in Diamond for each Port
sysConfig Port Diamond Default
1
CDONE_PORT CDONE_USER_IO
SLAVE_SPI_PORT Enable
I2C_PORT Disable
MASTER_SPI_PORT Disable
2
Note:
1. This default setting can be modified in the Diamond Spreadsheet View, Global Preferences tab.
2. The MASTER_SPI_PORT setting does not influence the behavior during configuration. For details, see the Configuration
section.
4.10.1. Self-Download Port Pins
CRESETB
The CRESETB is an active LOW input with a weak internal pull-up resistor used for configuration the FPGA. When
CRESETB is asserted LOW, the FPGA exits User Mode and starts a device configuration sequence at the Initialization
phase, as described in
Figure 4.1 . Holding the CRESETB pin LOW during power up keeps CrossLink in the Initialization
phase. This LOW period also allows an external SPI Master or I
2
C Master to write the Activation Key to the FPGA to
enter into slave configuration mode. The CRESETB has a minimum pulse width assertion period in order for it to be
recognized by the FPGA. You can find this minimum time in
CrossLink Family Data Sheet (FPGA-DS-02007) in the AC
timing section.
CRESETB
VCC
VCC min.
CRESETB transitions observed
Figure 4.2. Period CRESETB is Always Observed