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Lattice Semiconductor

Resource Utilization

IPUG39_02.9, December 2010

48

10 Gb+ Ethernet MAC IP Core User’s Guide

LatticeECP3 FPGAs

Table A-3. Performance and Resource Utilization

1

Ordering Part Number

The Ordering Part Number (OPN) for the 10 Gb+ Ethernet MAC IP core targeting LatticeECP3 devices is



ETHER-10G-E3-U4.

LatticeSC/M FPGAs

Table A-4. Performance and Resource Utilization

1

Ordering Part Number

The Ordering Part Number (OPN) for the 10 Gb+ Ethernet MAC IP core targeting LatticeSC/M devices is



ETHER-10G-SC-U4.

Mode

SLICEs

LUTs

Registers

External

Pins

2

sysMEM

EBRs

f

MAX

(MHz)

Multicast Address Filtering

3239

4024

2833

78

4

160

1. Performance and utilization data are generated using an LFE3-35EA-8FN672C device with Lattice’s Diamond 1.1 software with Synplify

Pro D-2010.03L-SP1 synthesis. Performance may vary when using a different software version or targeting a different device density or
speed grade within the LatticeECP3 family.

2. The 10 Gb+ Ethernet MAC core itself does not use any external pins. However, in an application the core is used together IODDR and I/O

Buffers integrated in the LatticeECP3 series FPGA. Thus the application implementing the 10 Gb+ Ethernet MAC specification will utilize
I/O pins.

Mode

SLICEs

LUTs

Registers

External

Pins

2

sysMEM

EBRs

f

MAX

(MHz)

Multicast Address Filtering

2961

4370

2764

78

4

205

1. Performance and utilization data are generated using an LFSC3GA25E-5F900C device with Lattice’s Diamond 1.1 software with Synplify

Pro D-2010.03L-SP1 synthesis. Performance may vary when using a different software version or targeting a different device density or
speed grade within the LatticeSC family.

2. The 10 Gb+ Ethernet MAC core itself does not use any external pins. However, in an application the core is used together IODDR and I/O

Buffers integrated in the LatticeSC series FPGA. Thus the application implementing the 10 Gb+ Ethernet MAC specification will utilize I/O
pins.

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Содержание 10 Gb+ Ethernet MAC IP

Страница 1: ...December 2010 IPUG39_02 9 10 Gb Ethernet MAC IP Core User s Guide...

Страница 2: ...Getting Started 16 IPexpress Created Files and Top Level Directory Structure 18 Instantiating the Core 20 Running Functional Simulation 20 Synthesizing and Implementing the Core in a Top Level Design...

Страница 3: ...Lattice Semiconductor Table of Contents IPUG39_02 9 December 2010 3 10 Gb Ethernet MAC IP Core User s Guide Ordering Part Number 48...

Страница 4: ...ted only on LatticeSC SCM XGMII interface to the PHY layer using IODDR external to the core XAUI interface to the PHY layer using PCS SERDES external to the core Simple FIFO interface with user s appl...

Страница 5: ...pports Full duplex operation Flow control using PAUSE frames VLAN tagged frames Automatic padding of short frames Optional FCS generation during transmission Optional FCS stripping during reception Ju...

Страница 6: ...15 0 tx_pausereq tx_force_err tx_byten 2 0 tx_is_paused tx_read rxmac_clk txmac_clk vlan_tag 15 0 vlan_tag_en mac_addr 47 0 mode 1 0 tx_cfg 3 0 rx_cfg 6 0 pause_opcode 15 0 tx_ipg 4 0 max_frm_len 13 0...

Страница 7: ...nterface XGMII PLL PLL 0 1 ODDR xgmii_tx_clk XGMII xgmii_rx_clk txmac_clk_ref SM I IODDR 10Gb MAC IP Core FPGA Top reset_n tx_data 63 0 tx_byten 2 0 tx_data_avail tx_force_err tx_paustim 15 0 tx_pausr...

Страница 8: ...e programmed to transfer the frame as it was received to the FIFO Promiscuous mode or after stripping off the FCS and any pad fields In all cases the SOF preamble and SFD bytes will always be stripped...

Страница 9: ...ticast frame is accepted if the bit selected from the hash table was set to one It is discarded if the bit selected was zero If the incoming frame had a broadcast address it will be accepted if the ei...

Страница 10: ...buses for transmit counters and receive counters The address bus is shared for transmit and receive counters The Statistics Counter is a part of the reference design A list of statistic counters is pr...

Страница 11: ...e frame tx_force_err High Input Indicates that the current frame has errors This input is qualified with input signal tx_eof tx_empty High Input When asserted indicates that the transmit FIFO is empty...

Страница 12: ...ddress AC DE 48 00 00 80 AC is sent first and 80 is sent last mode 1 0 High Input Bit 0 rx_en Enables the receive side of the MAC Bit 1 tx_en Enables the transmit side of the MAC tx_cfg 3 0 High Input...

Страница 13: ...Figure 2 7 Transmission of a 64 Data Byte Frame The tx_staten signal will be asserted once the entire frame is received from the user s interface Receive Interface When the MAC receives the data it a...

Страница 14: ...eters Figure 3 1 shows the 10 Gb Ethernet MAC IP Core configuration dialog box Figure 3 1 10 Gb Ethernet MAC IP Core Configuration Dialog Box Parameter Descriptions This section describes the availabl...

Страница 15: ...erface to conform to the XAUI definition a PCS SERDES quad is added at the top level of the FPGA when this core is implemented The top level file pro vided with this core contains the logic to impleme...

Страница 16: ...page 23 for further details However a license is required to enable timing simulation to open the design in the Diamond or ispLEVER EPIC tool and to generate bitstreams that do not include the hard wa...

Страница 17: ...Name default to the specified project parameters Refer to the IPexpress tool online help for further information To create a custom configuration the user clicks the Customize button in the IPexpress...

Страница 18: ...nfiguration GUI Diamond Version IPexpress Created Files and Top Level Directory Structure When the user clicks the Generate button in the IP Configuration dialog box the IP core and supporting files a...

Страница 19: ...name specified in the IPexpress tool Table 4 1 File List File Description username _inst v This file provides an instance template for the IP username v This file provides the 10 Gb Ethernet MAC core...

Страница 20: ...p v is logic memory and clock modules supporting an XGMII interface loop back capability a register module supporting programmable control of the 10 Gb Ethernet MAC core parameters and system processo...

Страница 21: ...layed in the Aldec Active HDL Wave window Synthesizing and Implementing the Core in a Top Level Design The 10 Gb Ethernet MAC IP core itself is synthesized and is provided in NGO format when the core...

Страница 22: ...username impl core_only synplify The user can run this tcl script to synthesize the core_only top_level files in the above directory For the reference project username _reference_top tcl will be gene...

Страница 23: ...Diamond To regenerate an IP core in Diamond 1 In IPexpress click the Regenerate button 2 In the Regenerate view of IPexpress choose the IPX source file of the module or IP you wish to regenerate 3 IPe...

Страница 24: ...rent settings for the IP core in the Source Value box Make your new settings in the Target Value box 4 If you want to generate a new set of files in a new location set the location in the LPC Target F...

Страница 25: ...s Reset Value Version Register VERID A00H X1H Mode Register MODE A01H 00H Transmit Control Register TX_CTL A02H 00H Receive Control Register RX_CTL A03H 00H Maximum Packet Size Register MAX_PKT_SIZE_0...

Страница 26: ...H Transmit Packet 512 1023 Statistics Counter TX_STAT_PKT_512_1023 888H 00H Transmit Packet 1024 1518 Statistics Counter TX_STAT_PKT_1024_1518 890H 00H Transmit Packet 1518 Statistics Counter TX_STAT_...

Страница 27: ...et Undersize Statistics Counter RX_PKT_UNDERSIZE 9a08H 00H Receive Packet Unicast Statistics Counter RX_PKT_UNICAST 9a8H 00H Packets Received Statistics Counter RX_PKT_RCVD 9b0H 00H Receive Packet 64...

Страница 28: ...PAUSE frame 0 Tx_pass_fcs R W 0 Transmit Pass FCS When set the FCS field generation is dis abled in the Tx MAC and the user is responsible to generate the appropriate FCS field Name RX_CTL Address A0...

Страница 29: ...dress 0x09 0x00 octet 3 to address 0x0A 0x00 octet 4 to address 0x0B and 0x80 octet 5 to address 0x0C Table 5 8 MAC Address Register Description Name MAX_PKT_SIZE Address A04H Bits Name Type Default D...

Страница 30: ...The frame is received only if this bit is set Table 5 11 Multicast Table Register Description Name TX_RX_STS Address A0DH Bits Name Type Default Description 7 5 UNUSED Reserved 4 Link_ok RO 0 Link OK...

Страница 31: ...PAUSE Opcode Upper byte 7 0 Pause_OpCode_1 R W 1 PAUSE Opcode Lower byte Name TSTCNTL Address B00H Bits Name Type Default Description 7 2 UNUSED Reserved 1 Loop back Enable R W 1 1 loop back 0 no loo...

Страница 32: ...Transmit Underrun Error Statistics Counter TX_STAT_UNDER_RUN A read of the low byte of this counter returns that byte and latches the upper bytes for later reading A read of any of the other bytes ret...

Страница 33: ...r that byte The low address addresses the low byte Table 5 24 Transmit Multicast Packet Statistics Counter Description Transmit Broadcast Packet Statistics Counter TX_STAT_BRDCST A read of the low byt...

Страница 34: ...byte and latches the upper bytes for later reading A read of any of the other bytes returns the previously latched value for that byte The low address addresses the low byte Table 5 29 Transmit VLAN...

Страница 35: ...nsmit Packet 128 255 Statistics Counter Description Transmit Packet 256 511 Statistics Counter TX_STAT_PKT_256_511 A read of the low byte of this counter returns that byte and latches the upper bytes...

Страница 36: ...byte Table 5 37 Transmit Packet 1518 Statistics Counter Description Transmit Frame Error Statistics Counter TX_STAT_FRM_ERR A read of the low byte of this counter returns that byte and latches the up...

Страница 37: ...4096 9216 Statistics Counter Description Transmit Packet 9217 16383 Statistics Counter TX_STAT_PKT_9217_16383 A read of the low byte of this counter returns that byte and latches the upper bytes for l...

Страница 38: ...r reading A read of any of the other bytes returns the previously latched value for that byte The low address addresses the low byte Table 5 46 Receive Filtered Packet Statistics Counter Description R...

Страница 39: ...escription Receive Long Packet Statistics Counter RX_STAT_LNG_PKT A read of the low byte of this counter returns that byte and latches the upper bytes for later reading A read of any of the other byte...

Страница 40: ...ed Statistics Counter Description Receive Packet Fragments Statistics Counter RX_PKT_FRAGMENTS A read of the low byte of this counter returns that byte and latches the upper bytes for later reading A...

Страница 41: ...t 128 255 Statistics Counter RX_PKT_128_255 A read of the low byte of this counter returns that byte and latches the upper bytes for later reading A read of any of the other bytes returns the previous...

Страница 42: ...Receive Packet Undersize Statistics Counter RX_PKT_UNDERSIZE A read of the low byte of this counter returns that byte and latches the upper bytes for later reading A read of any of the other bytes ret...

Страница 43: ...With Good CRC Statistics Counter RX_PKT_1518_GOOD_CRC A read of the low byte of this counter returns that byte and latches the upper bytes for later reading A read of any of the other bytes returns t...

Страница 44: ...ive Packet 9217 16383 Statistics Counter RX_PKT_9217_16383 A read of the low byte of this counter returns that byte and latches the upper bytes for later reading A read of any of the other bytes retur...

Страница 45: ...tline Receive direct technical support for all Lattice products by calling Lattice Applications from 5 30 a m to 6 p m Pacific Time For USA Canada 1 800 LATTICE 528 8423 For other locations 1 503 268...

Страница 46: ...P Core User s Guide to 10 Gb Ethernet MAC IP Core User s Guide Change all occurrences of 10G MAC to 10 Gb Ether net MAC Updated appendices for ispLEVER 7 1 software release October 2008 02 5 4 0 Added...

Страница 47: ...utilization data are generated using an LFE2 35E 7F672C device with Lattice s Diamond 1 1 software with Synplify Pro D 2010 03L SP1 synthesis Performance may vary when using a different software vers...

Страница 48: ...argeting a different device density or speed grade within the LatticeECP3 family 2 The 10 Gb Ethernet MAC core itself does not use any external pins However in an application the core is used together...

Страница 49: ...ry Lifecycle Information Lattice ETHER 10G P2 U3 ETHER 10G SC U3 ETHER 10G PM U3 ETHER 10G E3 U3 ETHER 10G P2 UT3 ETHER 10G PM UT3 ETHER 10G SC UT3 ETHER 10G E3 U4 ETHER 10G E3 UT4 ETHER 10G P2 U4 ETH...

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