POWER
AMPLIFIER
LOW
BAND
PUB96
‐
28
Rev
2
Aug.
2007
28-1
PA
Module,
Functional
Description
The
Power
Amplifier
module
consists
of
a
six
‐
way
power
splitter,
six
FET
amplifiers,
a
six
‐
way
power
combiner,
a
VSWR
protection
board,
and
power
&
I/O
connectors.
Two
full
‐
size
heatsinks
provide
the
cooling
for
the
active
devices.
It
is
designed
for
1.5
kW
sync
peak
power
output
in
Low
Band
54
‐
88
MHz
Analog
television
systems,
and
provides
power
gain
of
approximately
20
dB,
with
1.5
kW
peak
sync
visual
or
900
W
aural
output.
The
module
can
provide
upwards
of
250W
of
average
digital
power
when
used
with
appropriate
predistortion.
It
is
fully
hot
‐
pluggable,
incorporating
protective
circuitry
for
excess
VSWR
power
cutback.
6
‐
Way
Splitter/Input
Board
Part
number:
40D1474G1/40D1474G2
References:
Figure
3
and
Figure
4.
The
6
‐
Way
power
splitter
receives
its
RF
input
signal
from
the
drive
stage
and
provides
six
input
signals
to
integral
input
matching
networks
for
the
six
FET
amplifiers.
The
incoming
signal
is
first
split
in
three
by
a
3
‐
way
Wilkinson
splitter,
and
the
three
resultant
signals
are
split
again
by
three
2
‐
way
Wilkinson
splitters
to
provide
the
six
outputs
required.
Terminations
for
the
3
‐
way
splitter
are
provided
by
R109,
R110,
and
R111,
with
reactive
trimming
by
L109,
L110,
and
L111;
and
for
the
two
‐
way
splitters,
terminations
are
R101,
R103
and
R105,
with
reactive
trimming
by
C106,
C116,
and
C126.
Impedance
match
is
provided
by
C145,
C142,
C138,
C144,
C145,
C139,
and
C140
which
make
the
path
from
the
50
Ω
input
to
the
six
quarter
‐
wave
matching
sections,
into
a
low
‐
pass
π
network.
C148
provides
input
matching
for
the
transition
from
the
input
connector
to
the
input
transmission
line.
A
built
‐
in
detector
(CR102
and
C147)
is
fed
from
a
directional
coupler
on
the
input
transmission
line,
to
provide
a
sample
of
the
input
signal
for
module
gain
monitoring.
R117
and
R118
terminate
the
directional
coupler.
FET
RF
Amplifiers
References:
Figure
3,
Figure
4,
Figure
5,
Figure
6.
Each
of
the
six
amplifiers
in
the
module
consists
of
two,
source
grounded
N
‐
channel,
insulated
gate
Field
Effect
Transistors
(FETs)
packaged
in
a
single
case,
operating
class
AB
in
a
push
‐
pull
configuration.
Because
these
FETs
are
"enhancement
mode"
devices,
they
require
positive
gate
‐
to
‐
source
bias
voltage
on
each
gate
to
cause
source
‐
drain
conduction.
A
quiescent
Class
AB
idling
bias
current
is
set
independently
for
each
half.
The
gate
voltage
required
to
produce
this
idling
current
may
vary
between
2
V
and
5
V
according
to
the
device
specification
sheet,
and
the
idling
current
used.
FET
gate
threshold
voltages
also
are
temperature
sensitive,
so
thermal
compensation
is
provided
by
R9,
RT1,
and
R10,
RT2.
Bias
current
is
set
to
500mA
per
half
of
the
device
for
analog
operation
and
750mA
per
half
for
digital
operation.
Gate
bias
is
supplied
from
an
adjustable
voltage
divider
from
the
+39
V
regulated
bias
rail.
Resistors
R1,
R2,
R3,
R4
provide
gate
bias
for
one
half
of
the
amplifier;
R5,
R6,
R7,
R8
provide
bias
for
the
other
half.
The
RF
input
signal
is
applied
to
balun
T1
to
provide
two
signals
180
˚
out
‐
of
‐
phase.
These
signals
are
stepped
down
to
match
the
low
input
impedance
of
the
FET
device
through
a
π‐
network
consisting
of
C1,
C2,
C3,
L1,
L2,
C4,
and
the
device
CG
‐
S.
The
gate
input
impedance
at
the
operating
frequency
is
low
compared
with
the
values
of
R3
and
R6,
which
have
little
or
no
effect
at
RF.
