1 kW TTS1000B TRANSMITTER IPA ASSEMBLY
PUB96-30 rev 1: Jul 1, 2010
30-6
1 kW IPA Assembly VHF
High
Band
IPA
Circuit
Description
The
IPA
consists
of
two,
source
grounded
N
‐
channel,
insulated
gate
Field
Effect
Transistors
(FETs)
packaged
in
a
single
case,
and
operating
in
a
push
‐
pull
configuration
in
class
AB.
These
N
‐
channel
FETs
are
"enhancement
mode"
devices,
so
require
a
positive
gate
‐
to
‐
source
bias
voltage
on
each
gate
to
cause
source
‐
drain
conduction.
Quiescent
Class
AB
idling
bias
current
is
set
at
0.6
ampere
for
each
half.
The
gate
voltage
required
to
produce
this
idling
current
may
vary
between
2
and
5
V
due
to
variances
among
FETs,
and
typically
is
3
to
4
V.
Gate
voltages
also
are
temperature
sensitive,
so
temperature
compensation
is
provided
by
RT1
and
RT2.
Gate
bias
is
supplied
out
of
adjustable
voltage
dividers
from
+20
V
regulated
bias
sources
CR1
and
CR2.
Current
limiting
to
these
zener
diodes
is
provided
through
R2
and
R8.
Resistors
R9,
R1,
R3,
R4,
and
RT1
provide
gate
bias
for
the
"A"
half
of
the
amplifier;
R10,
R7,
R5,
R6,
and
RT2
provide
bias
for
the
"B"
half.
The
input
RF
arriving
in
J1
is
applied
to
balun
T1,
L1
to
provide
two
signal
outputs
180
°
out
of
phase.
These
signals
are
stepped
down
to
match
the
low
input
impedance
of
the
device
through
a
dual
section,
twin
π
network
consisting
of
C1,
C2,
L2,
L3,
C3,
and
the
device
input
capacitance,
and
then
applied
to
the
gates.
The
gate
impedance
at
the
operating
frequency
is
much
lower
than
R3
and
R5,
so
these
resistors
have
little
or
no
effect
at
RF.
R3
and
R5
provide
a
DC
path
for
bias,
and
provide
loading
at
lower
frequencies
in
order
to
assist
in
maintaining
amplifier
stability.
The
choice
of
C2
and
C6
values,
and
their
internal
equivalent
series
inductances,
also
ensures
effective
bypassing
at
critical
frequencies.
The
output
matching
π
network,
consisting
of
inductors
L5
thru
L10,
and
capacitances
C12
thru
C16,
tunes
out
the
FET
drain
capacitance
and
transforms
the
very
low
output
impedance
of
the
FET,
upwards
to
a
standard
50
ohms.
The
two
180
°
antiphase
output
signals
are
finally
combined
in
balun
T2,
L11.
DC
is
applied
to
the
drains
through
L4,
L5
for
the
"A"
half,
and
L6,
L7
for
the
"B"
half.
L5
and
L6
are
also
short
sections
of
microstrip
transmission
line
which
transform
the
apparent
RF
impedances
of
L4
and
L7
to
higher
values
seen
by
the
FET.
RF
and
lower
frequencies
are
bypassed
with
C1,
C10,
C11,
and
C8,
C9,
C7.
These
groups
of
capacitors
are
selected
in
value
and
for
their
internal
equivalent
series
inductances
so
that
they
will
be
an
effective
bypass
at
all
frequencies
of
interest
including
video,
to
assist
in
maintaining
stability.
Towards
this
objective
of
stability,
in
addition
to
resonating
with
the
device
drain
‐
to
‐
drain
capacitance
at
RF,
inductor
L9
places
a
heavy
load
on
the
FET
output
at
low
frequencies,
where
it
behaves
as
a
dead
short.
HB
IPA
Set
Up
Procedures
1.Set
up
a
50
V
power
supply,
current
limited
to
a
little
more
than
1.2
A.