1 kW TTS1000B TRANSMITTER IPA ASSEMBLY
PUB96-30 rev 1: Jul 1, 2010
30-3
1 kW IPA Assembly VHF
MRF
‐
151
‐
G
could
be
used
as
a
replacement
in
case
of
dire
emergency,
but
there
are
no
guarantees
as
to
its
performance.
Because
these
FETs
are
"enhancement
mode
N
‐
channel"
devices,
they
require
positive
gate
‐
to
‐
source
bias
voltage
on
each
gate
to
cause
source
‐
drain
conduction.
The
quiescent
Class
AB
idling
bias
current
is
set
at
0.6
ampere
for
each
half.
The
gate
voltage
required
to
produce
this
idling
current
may
vary
between
2
V
and
5
V
according
to
the
device
specification
sheet,
and
typically
is
3
to
4
V.
FET
gate
threshold
voltages
also
are
temperature
sensitive,
so
thermal
compensation
is
provided
by
RT1
and
RT2.
Gate
bias
is
supplied
out
of
adjustable
voltage
dividers
from
+20
V
regulated
bias
sources
CR1
and
CR2.
Current
limiting
to
these
zener
diodes
is
provided
through
R1
and
R8.
Resistors
R9,
R2,
R3,
R4,
and
RT1
provide
gate
bias
for
the
"A"
half
of
the
amplifier;
R10,
R7,
R6,
R5,
and
RT2
provide
bias
for
the
"B"
half.
The
RF
input
signal
arriving
in
J1
is
applied
to
balun
T1
to
provide
two
signals
180
°
out
‐
of
‐
phase.
These
antiphase
signals
are
stepped
down
to
match
the
low
input
impedance
of
the
FET
through
a
π‐
network
consisting
of
C1,
C2,
C3,
L1,
L2,
C4,
and
the
device
input
capacitance,
and
then
applied
to
the
gates.
The
capacitance
value
of
C4
is
changed
for
operation
on
channels
5
&
6.
The
gate
input
impedance
at
the
operating
frequency
is
low
compared
with
the
values
of
R3
and
R6,
which
have
little
or
no
effect
at
RF.
R3
and
R6
provide
a
DC
path
for
bias,
and
provide
loading
at
lower
frequencies
where
gate
impedance
is
high,
in
order
to
assist
in
maintaining
amplifier
stability.
The
choice
of
C6,
C7,
C20,
and
C21
values,
their
series
inductances,
and
that
of
board
traces,
also
ensures
effective
bypassing
at
critical
frequencies.
The
output
matching
π‐
network,
consisting
of
inductors
L3
thru
L8,
and
capacitances
C13
thru
C16,
transforms
the
very
low
output
impedance
of
the
FET,
upwards
to
a
standard
50
Ω
.
The
two
antiphase
output
signals
are
finally
combined
in
balun
T2,
L9.
Jumpers
placed
across
parts
of
L7
and
L8,
plus
the
changed
values
of
C13,
C14,
C15
and
C16,
configures
the
system
for
channels
5
&
6
operation.
DC
is
applied
to
the
FET
drains
through
L3,
L4
for
the
Q1A
half,
and
L5,
L6
for
the
Q1B
half.
L3
and
L6
are
short
sections
of
microstrip
line
which
transform
the
apparent
RF
impedances
of
L4
and
L5
to
higher
values
as
seen
by
the
FET.
RF
and
lower
frequencies
are
bypassed
with
paralleled
C9,
C10,
and
C17
for
the
"A"
half
of
the
amplifier,
and
C11,
C12,
and
C18
for
the
"B"
half.
These
groups
of
capacitors
are
selected
in
value
and
for
their
internal
equivalent
series
inductances
so
that
they
will
be
an
effective
bypass
at
critical
frequencies
of
interest,
including
video,
to
assist
in
maintaining
stability.
The
connections
for
C20
and
C21
also
assist
in
stability
due
to
their
return
paths
through
the
ground
plane
of
the
output
board.
This
connection
provides
a
small
amount
of
negative
feedback
as
a
primitive
means
of
neutralizing
the
amplifier.
The
RF
output
leaves
the
board
from
J2.
LB
IPA
Setup
Procedures
