Chapter 3. BISO Setup
27
User’s Manual
3.5 Advanced Chipset Setup
When you select the “ADVANCED CHIPSET SETUP” on the main program, the screen display will appears as:
Advanced Chipset Setup Screen
AMIBIOS SETUP – ADVANCED CHIPSET SETUP
© 2001 American Megatrends, Inc. All Rights Reserved
*******DRAM Timing******
SDRAM Frequency
Auto
Configure SDRAM Timing by SPD
Enabled
SDRAM CAS# Latency
3 Clocks
SDRAM RAS# Precharge
3 Clocks
SDRAM RAS# to CAS# Delay
3 Clocks
SDRAM Precharge Delay
7 Clocks
SDRAM Idle Timer
Infinite
SDRAM Read Thermal Management
Disabled
DRAM Integrity Mode
Disabled
Memory Hole
Disabled
APIC Interrupt Mode
Enabled
MPS Revision
1.4
AGP Aperture Size
64MB
USB Port 0&1
Disabled
USB Device Legacy Support
Disabled
ESC : Exit
-¯
: Sel
Port 64/60 Emulation
Disabled
PgUp/PgDn :
Modify
F1:Help
F2/F3 : Color
In the ‘Advanced Chipset Setup’ page, all options are predefined by the system board designer. Any attempt
to change the parameter of the fields are not recommended.
SDRAM Frequency:
This field displays the capability of the memory modules that you are using
--- Either PC100 or PC133
Configure SDRAM Timing by SPD:
Selects whether DRAM timing is controlled by the SPD (Serial Presence
Detect) EEPROM on the DRAM module. Setting to SPD enables CAS# Latency. RAS# Precharge, RAS# to CAS#
Delay and Precharge Delay automatically to be determined by BIOS based on the configurations on the SPD.
Selecting Manual allows users to configure these fields manually.
SDRAM CAS# Latency
This controls the timing delay(in clock cycles) before SDRAM starts a read
command after receiving it. Settings are 3 Clocks and 2 Clocks. 2 Clocks
increases the system performance while 3 Clocks provides more stable
performance.
SDRAM RAS# Precharge
This item controls the number of cycles for Row Address Strobe(RAS) to be
allowed to precharge. If insufficient time is allowed for the RAS to
accumulate its charge before DRAM refresh, refresh may be incomplete and
DRAM may fail to retain data. This item applies only when synchronous
DRAM is installed in the system. Available settings: 3 Clocks and 2 Clocks.
SDRAM RAS# to CAS# Delay This field allows you to set the number of cycle for a timing delay between
the CAS and RAS strobe signals, used when DRAM is written to, read from
or refreshed. Fast speed offers faster performance while slow speed offers
more stable performance. Settings: 3 Clocks and 2 Clocks.
SDRAM Precharge Delay
The field specifies the idle cycles before percharging an idle bank. Settings:
7 Clocks, 6 Clocks and 5 Clocks.
