SMARC-sAL28 User Guide. Rev. 1.0
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System Specifications
3.1.
Component Main Data
The table below summarizes the features of the motherboard.
Table 4: Component Main Data
SMARC-sAL28
Form factor
Smart Mobility Architecture (SMARC) Hardware with 82 mm x 50 mm, max. thickness
6
mm
Processor
NXP LS28 Layerscape SoC 1.3 GHz, 488 balls FC-BGA, 17x17 mm, 28 nm CMOS
Memory
DDR3L memory down. Maximum DDR3L memory size 8 GB.
Standard products with 2 GB and 4 GB are available.
For cost reductions lower memory sizes are possible.
Boot Flash
2 MB to 32 MB SPI NOR flash
Bootloader/BIOS
U-Boot Bootloader, Flash for Bootloader connected on SPI1(eSPI).
embedded
Multimedia Card
(eMMC)
8 GB pSLC and 32 GB pSLC on standard products
option for up to 64GB pSLC
EEPROM
24C32, 4k x 8 (32 kbit)
Temperature
Monitoring
Thermal Monitoring Unit (TMU) with +/- 5°C accuracy (CPU internal)
Thermal sensor measurement temperature range is 0°C to 125°C.
Onboard Controllers
Ethernet Controller
2x 1 GBE PHY Qualcomm AR8031-AL, WOL support
1st PHY via SGMII or RGMII BOM option
2nd PHY as BOM option via SGMII
Watchdog
CPU internal watchdog
CPLD watchdog for WDT_TIME_OUT#
RTC
High accuracy (+/-3
ppm
)
Low power consumption: current consumption typical below 1 μA
USB HUB
7 port USB HUB Microchip USB2517I
Display bridge
Optional: Display Port to LVDS converter PTN3460I
System
Management
Controller
CPLD Intel/Altera MAX V 5M570Z
Security
Optional: APPROTECT Key 1504-03 connected via USB, no SPI connection
Power
management
CPLD controls payload power down state
Operating System
Support
Linux Yocto
Buildroot (https://github.com/kontron/buildroot-external-smarc-sal28)
other Operating Systems on customer request
Interfaces via Smarc I/O
USB
USB0, USB1, USB2, USB3, USB4, USB5: USB Standard 2.0
USB3: USB Standard 3.1 GEN1 with OTG support
PCIe
4x configurable SERDES lines. Line A and B always present. C and D either used for on
module LAN PHYs or as SGMII/XGMII on the carrier (resistor BOM options)
Up to 2x PCIe controller
Audio
I2S0
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