Kontron mITX-BDW-U, Руководство пользователя

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mITX-BDW-U – User Guide, Rev. 1.6
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7.11. LVDS Flat Panel Connector (J33)
The LVDS connector (J33) is based on a 40-pin connector type Don Connex C44-40BSB1-G.
lVDS Connector Pinout
Note Type Signal PIN Signal Type Note
Max. 0.5 A PWR +12 V 1 2 +12 V PWR Max. 0.5 A
Max. 0.5 A PWR +12 V 3 4 +12 V PWR Max. 0.5 A
Max. 0.5 A PWR +12 V 5 6 GND PWR Max. 0.5 A
Max. 0.5 A PWR +5 V 7 8 GND PWR Max. 0.5 A
Max. 0.5 A PWR LCDVCC 9 10 LCDVCC PWR Max. 0.5 A
2K2Ω, 3.3 V OT DDC CLK 11 12 DDC DATA OT 2.2 KΩ, 3.3 V
3.3 V level OT BKLTCTL 13 14 VDD ENABLE OT 3.3 V level
3.3 V level OT BKLTEN# 15 16 GND PWR Max. 0.5 A
LVDS LVDS A0- 17 18 LVDS A0+ LVDS
LVDS LVDS A1- 19 20 LVDS A1+ LVDS
LVDS LVDS A2- 21 22 LVDS A2+ LVDS
LVDS LVDS ACLK- 23 24 LVDS ACLK+ LVDS
LVDS LVDS A3- 25 26 LVDS A3+ LVDS
Max. 0.5 A PWR GND 27 28 GND PWR Max. 0.5 A
LVDS LVDS B0- 29 30 LVDS B0+ LVDS
LVDS LVDS B1- 31 32 LVDS B1+ LVDS
LVDS LVDS B2- 33 34 LVDS B2+ LVDS
LVDS LVDS BCLK- 35 36 LVDS BCLK+ LVDS
LVDS LVDS B3- 37 38 LVDS B3+ LVDS
Max. 0.5 A PWR GND 39 40 GND PWR Max. 0.5 A
The LVDS connector supports single and dual channel, 18/24 bit SPWG panels, up to a
resolution of 1600x1200 or 1920x1080, and with limited frame rate up to 1920x1200.
Signal Description
LVDS A0..A3 LVDS A Channel data
LVDS ACLK LVDS A Channel clock
LVDS B0..B3 LVDS B Channel data
LVDS BCLK LVDS B Channel clock
BKLTCTL Backlight control (1), PWM signal to implement voltage in the range 0-3.3 V
BKLTEN# Backlight Enable signal (active low) (2)
VDD ENABLE Output Display Enable.
LCDVCC 5 V or 3.3 V VCC supply to the display, (1 A Maximum)
Selected in BIOS setup menu ( Advanced > Display Configuration> Panel VCC)
Power sequencing depends on LVDS panel selection, (Shared with eDP connector)
DDC CLK DDC Channel Clock
Windows API will be available to operate the BKLTCTL signal. Some Inverters have a limited
voltage range 0- 2.5 V for this signal: If the voltage is > 2.5 V the Inverter might latch up.
Some Inverters generate noise on the BKLTCTL signal, causing the LVDS transmission to fail
(corrupted picture on the display). By adding a 1 Kohm resistor in series with this signal,
mounted at the Inverter end of the cable kit, the noise is limited and the picture is stable.
If the Backlight Enable is required to be active high, check the following BIOS Chipset setting:
Backlight Signal Inversion = Enabled.
7.12. Feature Connector (J28)