Kontron 786LCD/mITX, Руководство пользователя

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786LCD/mITX Family
KTD-00629-K Public User Manual Date: 2009-10-13 Page 26 of 77
Signal Description – AGP Connector:
Signal Description
Address
PIPE# Pipeline.
During PIPE# Operation.
This signal is asserted by the AGP master to
indicate a full-width address is to be enqueued on by the target using the AD
bus. One address is placed in the AGP request queue on each rising clock
edge while PIPE# is asserted.
During SBA Operation.
This signal is not used if SBA (Side Band
Addressing) is selected.
During FRAME# Operation.
Not used.
SBA[7:0] Side-band Addressing.
During PIPE# Operation.
Not used.
During SBA Operation.
These signals (the SBA, or side-band addressing,
bus) are used by the AGP master (graphics component) to place addresses
into the AGP request queue. The SBA bus and AD bus operate
independently. That is, transactions can proceed on the SBA bus and the AD
bus simultaneously.
During FRAME# Operation.
Not used.
Flow control
RBF# Read Buffer Full.
During PIPE# and SBA Operation.
Read buffer full indicates if the master is
ready to accept previously requested low priority read data. When R
BF#
is
asserted the GMCH is not allowed to initiate the return low priority read data.
That is, the GMCH can finish returning the data for the request currently
being serviced, however it cannot begin returning data for the next request.
RBF# is only sampled at the beginning of a cycle.
If the AGP master is always ready to accept return read data, then it is not required to implement
this signal.
During FRAME# Operation.
This signal is not used during AGP FRAME# operation.
WBF# Write-Buffer Full.
During PIPE# and SBA Operation.
Write buffer full indicates if the master is
ready to accept Fast Write data from the GMCH. When W
BF#
is asserted
the GMCH is not allowed to drive Fast Write data to the AGP master. WBF#
is only sampled at the beginning of a cycle.
If the AGP master is always ready to accept fast write data, then it is not
required to implement this signal.
During FRAME# Operation
: This signal is not used during AGP FRAME# operation.
AGP Status
ST[2:0] Status Bus.
During PIPE# and SBA Operation.
Provides information from the arbiter to an AGP Master on
what it may do. ST[2:0] only have meaning to the master when its GNT# is asserted. When
GNT# is deasserted, these signals have no meaning and must be ignored. Refer to the AGP
Interface Specification revision 2.0 for further explanation of the ST[2:0] values and their
meanings.
During FRAME# Operation.
These signals are not used during FRAME# based operation;
except that a ‘111’ indicates that the master may begin a FRAME# transaction.
AGP Strobes
ADSTB[0] Address/Data Bus Strobe-0:
provides timing for 2x and 4x data on
AD[15:0]
and
C/BE[1:0]#
signals. The agent that is providing the data will drive this signal.
ADSTB#[0] Address/Data Bus Strobe-0 Complement:
With AD STB0, forms a differential strobe pair that
provides timing information for the
AD[15:0]
and
C/BE[1:0]#
signals. The agent that is providing
the data will drive this signal.
ADSTB[1] Address/Data Bus Strobe-1:
Provides timing for 2x and 4x data on
AD[31:16]
and
C/BE[3:2]#
signals. The agent that is providing the data will drive this signal.
ADSTB#[1] Address/Data Bus Strobe-1 Complement:
With AD STB1, forms a differential strobe pair that
provides timing information for the AD[15:0] and C/BE[1:0]# signals in 4X mode. The agent that
is providing the data will drive this signal.
SBSTB Sideband Strobe:
Provides timing for 2x and 4x data on the
SBA[7:0]
bus. It is driven by the
AGP master after the system has been configured for 2x or 4x sideband address mode.
SBSTB# Sideband Strobe Complement:
The differential complement to the
SB_STB
signal. It is used to
provide timing 4x mode.
AGP/PCI Signals-Semantics
FRAME# G_FRAME:
Frame.
During PIPE# and SBA Operation:
Not used by AGP SBA and PIPE# operations.
During Fast Write Operation:
Used to frame transactions as an output during Fast
Writes.