
M T D / P S - 0 7 1 5
R e v i s i o n
4 . 0
w w w . k o d a k . c o m / g o / i m a g e r s 5 8 5 - 7 2 2 - 4 3 8 5 F a x : 5 8 5 - 4 7 7 - 4 9 4 7 E m a i l : i m a g e r s @ k o d a k . c o m
P a g e 2 o f 3 1
IMAGE SENSOR SOLUTIONS
TABLE OF CONTENTS
KAI-2001/KAI-2020/KAI-2093 IMAGER EVALUATION BOARD DESCRIPTION ......... 3
IMAGER BOARD INPUT REQUIREMENTS .................................................................. 3
KAI-2001/KAI-2020/KAI-2093 IMAGER BOARD ARCHITECTURE OVERVIEW.......... 5
P
OWER
F
ILTERING
A
ND
R
EGULATION
............................................................................................................ 5
LVDS R
ECEIVERS
/ TTL B
UFFERS
............................................................................................................... 5
CCD P
IXEL
-R
ATE
C
LOCK
D
RIVERS
(H1, H2 & R
ESET
C
LOCKS
).................................................................... 5
R
ESET
C
LOCK
O
NE
-S
HOT
............................................................................................................................. 5
CCD VCLK
D
RIVERS
................................................................................................................................... 5
CCD FDG DRIVER..................................................................................................................................... 5
VSUB/VES CIRCUIT.................................................................................................................................. 5
VDD B
IAS
V
OLTAGE
.................................................................................................................................... 5
ESD B
IAS
V
OLTAGE
..................................................................................................................................... 6
CCD I
MAGE
S
ENSOR
.................................................................................................................................... 6
E
MITTER
-F
OLLOWER
.................................................................................................................................... 6
L
INE
D
RIVERS
............................................................................................................................................... 6
KAI-2001/KAI-2020/KAI-2093 OPERATIONAL SETTINGS .......................................... 7
DC B
IAS
V
OLTAGES
..................................................................................................................................... 7
C
LOCK
V
OLTAGES
........................................................................................................................................ 7
R
ESET
C
LOCK
P
ULSE
W
IDTH
........................................................................................................................ 8
BLOCK DIAGRAM AND PERFORMANCE DATA......................................................... 9
CONNECTOR ASSIGNMENTS AND PINOUTS .......................................................... 11
SMB
C
ONNECTORS
J1, J2
AND
J3............................................................................................................. 11
B
OARD
I
NTERFACE
C
ONNECTOR
J4 ............................................................................................................ 11
WARNINGS AND ADVISORIES .................................................................................. 12
REFERENCES.............................................................................................................. 12
GLOSSARY OF ABBREVIATIONS.............................................................................. 12
REVISION HISTORY .................................................................................................... 12
APPENDICES............................................................................................................... 13
KAI-2001/KAI-2020/KAI-2093 I
MAGER
B
OARD
S
CHEMATICS
.................................................................... 13
TABLES
Table 1: Power Requirements.................................................................................................................... 3
Table 2: Signal Level Requirements ......................................................................................................... 4
Table 3: DC Bias Voltages.......................................................................................................................... 7
Table 4: Clock Voltages.............................................................................................................................. 7
Table 5: Reset Clock Pulse Width ............................................................................................................. 8
Table 6: J4 Interface Connector Pin Assignments ................................................................................ 11
FIGURES
Figure 1. KAI-2001/KAI-2020/KAI-2093 Imager Board Block Diagram ................................................... 9
Figure 2. Measured Performance -- Dynamic Range and Noise Floor ................................................ 10
Содержание KAI-2001
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