
M T D / P S - 0 7 1 5
R e v i s i o n
4 . 0
w w w . k o d a k . c o m / g o / i m a g e r s 5 8 5 - 7 2 2 - 4 3 8 5 F a x : 5 8 5 - 4 7 7 - 4 9 4 7 E m a i l : i m a g e r s @ k o d a k . c o m
P a g e 1 2 o f 3 1
IMAGE SENSOR SOLUTIONS
WARNINGS AND ADVISORIES
The Imager Board described in this document is designed to be used as part of a two-board set, in
conjunction with a Timing Generator Board. Kodak offers an Imager Board / Timing Generator Board
package that has been designed and configured to operate with the KAI-2001, KAI-2020, and KAI-2093
CCD image sensors.
Purchasers of a Kodak Evaluation Board Kit may, at their discretion, make changes to the Timing
Generator Board firmware. Eastman Kodak can only support firmware developed by, and supplied by,
Eastman Kodak. Changes to the firmware are at the risk of the customer.
When programming the Timing Board, the Imager Board should be disconnected from the Timing Board,
by removing the Board Interface Cable before power is applied. If the Imager Board is connected to the
Timing Board during the reprogramming of the Altera PLD, damage to the Imager Board may occur.
When applying power to the Evaluation Board Kit, care should be taken that the VMINUS supply is
applied before, or simultaneously with, the other power supplies.
REFERENCES
1. KAI-2001 CCD Image Sensor Device Performance Specification
2. KAI-2020 CCD Image Sensor Device Performance Specification
3. KAI-2093 CCD Image Sensor Device Performance Specification
Kodak reserves the right to change any information contained herein without notice. All information
furnished by Kodak is believed to be accurate.
GLOSSARY OF ABBREVIATIONS
AGND Analog
Ground.
CCD
Charge-Coupled Device; also referred as to the image sensor , imager, or device.
FDG
Fast Dump Gate; signal drains charge from the Horizontal registers to allow line sampling.
HCLK Horizontal
Clock
LVDS
Low Voltage Differential Signaling, per the TIA/EIA-644 and IEEE 1596.3 standards.
R+ or R- Reset Clock
SMB
Subminiature video connector, 75
Ω
characteristic impedance.
VCLK Vertical
Clock.
V3RD Vertical
Clock
3
rd
-level voltage; initiates frame readout by transferring charge to vertical registers.
VES
Electronic Shutter control signal.
REVISION HISTORY
Revision
Number
Description of Changes
1
Initial Formal Version
2
Revision 2 Product Drawing; change to FD_HIGH limits (Table 4)
3
Revision 3 Product Drawing; added KAI-2001 CCD. (3F5121 assembly is still Rev 2)
4.0
Revision 4 Product Drawing; added KAI-2093 CCD. (3F5121 assembly is Rev 4)
Содержание KAI-2001
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