Keysight M9005A PXIe Chassis User Guide
11
M9005A Chassis Backplane Overview
Getting Started
PXI_CLK10, PXIE_CLK100, and PXIE_SYNC100 are driven to every peripheral slot
and have the default timing relationship described in
Figure 7
System Reference Clock Default Behavior
PXIe_CLK100
PXI_CLK10
PXIe_SYNC100
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
Содержание M9005A
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